On Mon, Sep 28, 2020 at 4:03 PM Ferruh Yigit <ferruh.yi...@intel.com> wrote:
>
> On 9/28/2020 9:59 AM, David Marchand wrote:
> > On Sun, Sep 27, 2020 at 2:21 PM Jerin Jacob <jerinjac...@gmail.com> wrote:
> >>
> >> On Fri, Sep 25, 2020 at 5:26 PM Manish Chopra <mani...@marvell.com> wrote:
> >>>
> >>> By adding generic API, this patch removes individual
> >>> functions/defines implemented by drivers to find extended
> >>> PCI capabilities.
> >>>
> >>> Signed-off-by: Manish Chopra <mani...@marvell.com>
> >>> Signed-off-by: Igor Russkikh <irussk...@marvell.com>
> >>> Reviewed-by: Gaetan Rivet <gr...@u256.net>
> >>
> >> Reviewed-by: Jerin Jacob <jer...@marvell.com>
> >>
> >> @Thomas Monjalon @David Marchand @Ferruh Yigit
> >>
> >> Othe patches in the qede series is depending on this patch, Let me
> >> know, how we are planning to pull this patch? Is through main or
> >> dpdk-next-net or dpdk-next-net-mrvl?
> >
> > Just two small comments, that can be fixed by whoever applies it.
> >
> > - The title does not reflect that we are adding an API to the pci bus.
> > My suggestion is: "bus/pci: query PCI extended capabilities"
> >
> > - There is an unneeded empty line added to lib/librte_pci/rte_pci.h:
> > diff --git a/lib/librte_pci/rte_pci.h b/lib/librte_pci/rte_pci.h
> > index 1d89651ec8..f89c7dbbea 100644
> > --- a/lib/librte_pci/rte_pci.h
> > +++ b/lib/librte_pci/rte_pci.h
> > @@ -22,7 +22,6 @@ extern "C" {
> > #include <inttypes.h>
> > #include <sys/types.h>
> >
> > -
> > /*
> > * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
> > * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
> >
> >
> > The patch is reviewed by Gaëtan.
> > Either through next-net or next-net-mrvl is fine to me.
> >
> > I'll leave the decision to Ferruh.
> >
> >
>
> Since other patches in the set requires Jerin's review,
> @Jerin can you get the patchset to dpdk-next-net-mrvl?
Yes. Merged the series after addressing @David Marchand's comments.
Series applied to dpdk-next-net-mrvl/master. Thanks.
