> > > > > > > > Using 'rte_mb' to synchronize the shared ring head/tail between > > > > producer and consumer will stall the pipeline and damage > > > > performance on the weak memory model platforms, such like aarch64. > > > > > > > > Relax the expensive barrier with c11 atomic with explicit memory > > > > ordering can improve 3.6% performance on throughput. > > > > My question here is: `rte_mb` is supposed to make sure that head/tail > > pointer are not updated before the packets are written into shared > memory. > > Does the atomic ensures that the packets are written into shared > > memory before head/tail pointers are updated? > > Yes, it does. > The atomic store-release acts as a one-way barrier here to make sure all the > memory accesses before the store-release are observed before it.
Ok then, since the sync is there and the rest seems fine to me. Thanks, Jakub Reviewed-by: Jakub Grajciar <jgraj...@cisco.com>
