On 9/2/20 10:34 AM, Matan Azrad wrote:
> The CQ configuration enables the collapse feature in HW what cause HW to
> write all the completions in the first CQE.
> When this feature is enabled the HW doesn't switch the owner bit when it
> starts a new cycle of the CQ, not like working without the collapse
> feature.
>
> The current SW CQ polling wrongly added an assertion to validate the
> owner bit switch what causes a panic in debug mode.
>
> Remove the aforementioned assertion.
>
> Fixes: c5f714e50b0e ("vdpa/mlx5: optimize completion queue poll")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Matan Azrad <ma...@nvidia.com>
> Acked-by: Xueming Li <xuemi...@nvidia.com>
> ---
> drivers/vdpa/mlx5/mlx5_vdpa_event.c | 2 --
> 1 file changed, 2 deletions(-)
Applied to dpdk-next-virtio/master.
Thanks,
Maxime
