<snip>
>
> Remove the deprecated rte_cio_[rw]mb APIs.
>
> Signed-off-by: Phil Yang <phil.y...@arm.com>
> Reviewed-by: Ruifeng Wang <ruifeng.w...@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagaraha...@arm.com>
> ---
> doc/guides/rel_notes/release_20_11.rst | 3 +++
> lib/librte_eal/arm/include/rte_atomic_32.h | 4 ---
> lib/librte_eal/arm/include/rte_atomic_64.h | 4 ---
> lib/librte_eal/include/generic/rte_atomic.h | 39 -----------------------------
> lib/librte_eal/ppc/include/rte_atomic.h | 4 ---
> lib/librte_eal/x86/include/rte_atomic.h | 4 ---
> 6 files changed, 3 insertions(+), 55 deletions(-)
>
> diff --git a/doc/guides/rel_notes/release_20_11.rst
> b/doc/guides/rel_notes/release_20_11.rst
> index df227a1..7090caf 100644
> --- a/doc/guides/rel_notes/release_20_11.rst
> +++ b/doc/guides/rel_notes/release_20_11.rst
> @@ -84,6 +84,9 @@ API Changes
> Also, make sure to start the actual text at the margin.
> =======================================================
>
> +* eal: The ``rte_cio_rmb()`` and ``rte_cio_wmb()`` were deprecated
> +since
> + 20.08 and are removed in this release.
> +
>
> ABI Changes
> -----------
> diff --git a/lib/librte_eal/arm/include/rte_atomic_32.h
> b/lib/librte_eal/arm/include/rte_atomic_32.h
> index 368f10c..9d0568d 100644
> --- a/lib/librte_eal/arm/include/rte_atomic_32.h
> +++ b/lib/librte_eal/arm/include/rte_atomic_32.h
> @@ -33,10 +33,6 @@ extern "C" {
>
> #define rte_io_rmb() rte_rmb()
>
> -#define rte_cio_wmb() rte_wmb()
> -
> -#define rte_cio_rmb() rte_rmb()
> -
> static __rte_always_inline void
> rte_atomic_thread_fence(int memory_order) { diff --git
> a/lib/librte_eal/arm/include/rte_atomic_64.h
> b/lib/librte_eal/arm/include/rte_atomic_64.h
> index 5cae52d..c518559 100644
> --- a/lib/librte_eal/arm/include/rte_atomic_64.h
> +++ b/lib/librte_eal/arm/include/rte_atomic_64.h
> @@ -37,10 +37,6 @@ extern "C" {
>
> #define rte_io_rmb() rte_rmb()
>
> -#define rte_cio_wmb() rte_wmb()
> -
> -#define rte_cio_rmb() rte_rmb()
> -
> static __rte_always_inline void
> rte_atomic_thread_fence(int memory_order) { diff --git
> a/lib/librte_eal/include/generic/rte_atomic.h
> b/lib/librte_eal/include/generic/rte_atomic.h
> index 95270f1..d1255b2 100644
> --- a/lib/librte_eal/include/generic/rte_atomic.h
> +++ b/lib/librte_eal/include/generic/rte_atomic.h
> @@ -107,45 +107,6 @@ static inline void rte_io_wmb(void); static inline
> void rte_io_rmb(void); ///@}
>
> -/** @name Coherent I/O Memory Barrier
> - *
> - * Coherent I/O memory barrier is a lightweight version of I/O memory
> - * barriers which are system-wide data synchronization barriers. This
> - * is for only coherent memory domain between lcore and I/O device but
> - * it is same as the I/O memory barriers in most of architectures.
> - * However, some architecture provides even lighter barriers which are
> - * somewhere in between I/O memory barriers and SMP memory barriers.
> - * For example, in case of ARMv8, DMB(data memory barrier) instruction
> - * can have different shareability domains - inner-shareable and
> - * outer-shareable. And inner-shareable DMB fits for SMP memory
> - * barriers and outer-shareable DMB for coherent I/O memory barriers,
> - * which acts on coherent memory.
> - *
> - * In most cases, I/O memory barriers are safer but if operations are
> - * on coherent memory instead of incoherent MMIO region of a device,
> - * then coherent I/O memory barriers can be used and this could bring
> - * performance gain depending on architectures.
> - */
> -///@{
> -/**
> - * Write memory barrier for coherent memory between lcore and I/O
> device
> - *
> - * Guarantees that the STORE operations on coherent memory that
> - * precede the rte_cio_wmb() call are visible to I/O device before the
> - * STORE operations that follow it.
> - */
> -static inline void rte_cio_wmb(void);
> -
> -/**
> - * Read memory barrier for coherent memory between lcore and I/O device
> - *
> - * Guarantees that the LOAD operations on coherent memory updated by
> - * I/O device that precede the rte_cio_rmb() call are visible to CPU
> - * before the LOAD operations that follow it.
> - */
> -static inline void rte_cio_rmb(void);
> -///@}
> -
> #endif /* __DOXYGEN__ */
>
> /**
> diff --git a/lib/librte_eal/ppc/include/rte_atomic.h
> b/lib/librte_eal/ppc/include/rte_atomic.h
> index 527fcaf..a919899 100644
> --- a/lib/librte_eal/ppc/include/rte_atomic.h
> +++ b/lib/librte_eal/ppc/include/rte_atomic.h
> @@ -36,10 +36,6 @@ extern "C" {
>
> #define rte_io_rmb() rte_rmb()
>
> -#define rte_cio_wmb() rte_wmb()
> -
> -#define rte_cio_rmb() rte_rmb()
> -
> static __rte_always_inline void
> rte_atomic_thread_fence(int memory_order) { diff --git
> a/lib/librte_eal/x86/include/rte_atomic.h
> b/lib/librte_eal/x86/include/rte_atomic.h
> index 62ea393..b7d6b06 100644
> --- a/lib/librte_eal/x86/include/rte_atomic.h
> +++ b/lib/librte_eal/x86/include/rte_atomic.h
> @@ -79,10 +79,6 @@ rte_smp_mb(void)
>
> #define rte_io_rmb() rte_compiler_barrier()
>
> -#define rte_cio_wmb() rte_compiler_barrier()
> -
> -#define rte_cio_rmb() rte_compiler_barrier()
> -
> /**
> * Synchronization fence between threads based on the specified memory
> order.
> *
> --
> 2.7.4
