The crypto adapter callback functions and associated data structures
are added.
Signed-off-by: Ankur Dwivedi <adwiv...@marvell.com>
---
drivers/crypto/octeontx2/meson.build | 4 +-
.../crypto/octeontx2/otx2_crypto_adapter.c | 77 +++++++++++++++++++
.../crypto/octeontx2/otx2_crypto_adapter.h | 21 +++++
.../octeontx2/otx2_cryptodev_hw_access.h | 12 +++
drivers/crypto/octeontx2/otx2_cryptodev_qp.h | 7 ++
.../rte_pmd_octeontx2_crypto_version.map | 10 +++
drivers/event/octeontx2/meson.build | 2 +-
drivers/event/octeontx2/otx2_evdev.c | 5 ++
8 files changed, 136 insertions(+), 2 deletions(-)
create mode 100644 drivers/crypto/octeontx2/otx2_crypto_adapter.c
create mode 100644 drivers/crypto/octeontx2/otx2_crypto_adapter.h
diff --git a/drivers/crypto/octeontx2/meson.build
b/drivers/crypto/octeontx2/meson.build
index 148ec184a..063a553f2 100644
--- a/drivers/crypto/octeontx2/meson.build
+++ b/drivers/crypto/octeontx2/meson.build
@@ -10,6 +10,7 @@ deps += ['bus_pci']
deps += ['common_cpt']
deps += ['common_octeontx2']
deps += ['ethdev']
+deps += ['eventdev']
deps += ['security']
name = 'octeontx2_crypto'
@@ -18,7 +19,8 @@ sources = files('otx2_cryptodev.c',
'otx2_cryptodev_hw_access.c',
'otx2_cryptodev_mbox.c',
'otx2_cryptodev_ops.c',
- 'otx2_cryptodev_sec.c')
+ 'otx2_cryptodev_sec.c',
+ 'otx2_crypto_adapter.c')
extra_flags = []
# This integrated controller runs only on a arm64 machine, remove 32bit
warnings
diff --git a/drivers/crypto/octeontx2/otx2_crypto_adapter.c
b/drivers/crypto/octeontx2/otx2_crypto_adapter.c
new file mode 100644
index 000000000..cfde7ec4f
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_crypto_adapter.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <rte_cryptodev.h>
+#include <rte_eventdev.h>
+
+#include "otx2_cryptodev_hw_access.h"
+#include "otx2_cryptodev_qp.h"
+#include "otx2_cryptodev_mbox.h"
+#include "otx2_crypto_adapter.h"
+
+int
+otx2_ca_caps_get(const struct rte_eventdev *dev,
+ const struct rte_cryptodev *cdev, uint32_t *caps)
+{
+ RTE_SET_USED(dev);
+ RTE_SET_USED(cdev);
+
+ *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND |
+ RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW;
+
+ return 0;
+}
+
+int
+otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev
*cdev,
+ int32_t queue_pair_id, const struct rte_event *event)
+{
+ union otx2_cpt_af_lf_ctl2 af_lf_ctl2;
+ struct otx2_cpt_qp *qp;
+ int ret;
+
+ RTE_SET_USED(dev);
+
+ qp = cdev->data->queue_pairs[queue_pair_id];
+
+ qp->ca_enable = 1;
+ rte_memcpy(&qp->ev, event, sizeof(struct rte_event));
+
+ ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),
+ &af_lf_ctl2.u);
+ if (ret)
+ return ret;
+
+ af_lf_ctl2.s.sso_pf_func = otx2_sso_pf_func_get();
+ ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),
+ af_lf_ctl2.u);
+
+ return ret;
+}
+
+int
+otx2_ca_qp_del(const struct rte_eventdev *dev, const struct rte_cryptodev
*cdev,
+ int32_t queue_pair_id)
+{
+ union otx2_cpt_af_lf_ctl2 af_lf_ctl2;
+ struct otx2_cpt_qp *qp;
+ int ret;
+
+ RTE_SET_USED(dev);
+
+ qp = cdev->data->queue_pairs[queue_pair_id];
+ qp->ca_enable = 0;
+ memset(&qp->ev, 0, sizeof(struct rte_event));
+
+ ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),
+ &af_lf_ctl2.u);
+ if (ret)
+ return ret;
+
+ af_lf_ctl2.s.sso_pf_func = 0;
+ ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),
+ af_lf_ctl2.u);
+
+ return ret;
+}
diff --git a/drivers/crypto/octeontx2/otx2_crypto_adapter.h
b/drivers/crypto/octeontx2/otx2_crypto_adapter.h
new file mode 100644
index 000000000..c8f02c0af
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_crypto_adapter.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTO_ADAPTER_H_
+#define _OTX2_CRYPTO_ADAPTER_H_
+
+__rte_internal
+int otx2_ca_caps_get(const struct rte_eventdev *dev,
+ const struct rte_cryptodev *cdev, uint32_t *caps);
+
+__rte_internal
+int otx2_ca_qp_add(const struct rte_eventdev *dev,
+ const struct rte_cryptodev *cdev, int32_t queue_pair_id,
+ const struct rte_event *event);
+
+__rte_internal
+int otx2_ca_qp_del(const struct rte_eventdev *dev,
+ const struct rte_cryptodev *cdev, int32_t queue_pair_id);
+
+#endif /* _OTX2_CRYPTO_ADAPTER_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
index 43db6a642..a435818e0 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
@@ -42,6 +42,7 @@
#define OTX2_CPT_LF_NQ(a) (0x400ull | (uint64_t)(a) << 3)
#define OTX2_CPT_AF_LF_CTL(a) (0x27000ull | (uint64_t)(a) << 3)
+#define OTX2_CPT_AF_LF_CTL2(a) (0x29000ull | (uint64_t)(a) << 3)
#define OTX2_CPT_LF_BAR2(vf, q_id) \
((vf)->otx2_dev.bar2 + \
@@ -110,6 +111,17 @@ union otx2_cpt_af_lf_ctl {
} s;
};
+union otx2_cpt_af_lf_ctl2 {
+ uint64_t u;
+ struct {
+ uint64_t exe_no_swap : 1;
+ uint64_t exe_ldwb : 1;
+ uint64_t reserved_2_31 : 30;
+ uint64_t sso_pf_func : 16;
+ uint64_t nix_pf_func : 16;
+ } s;
+};
+
union otx2_cpt_lf_q_grp_ptr {
uint64_t u;
struct {
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h
b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h
index 9d48da45f..96ff4eb41 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h
@@ -6,6 +6,7 @@
#define _OTX2_CRYPTODEV_QP_H_
#include <rte_common.h>
+#include <rte_eventdev.h>
#include <rte_mempool.h>
#include <rte_spinlock.h>
@@ -30,6 +31,12 @@ struct otx2_cpt_qp {
/**< Metabuf info required to support operations on the queue pair */
rte_iova_t iq_dma_addr;
/**< Instruction queue address */
+ struct rte_event ev;
+ /**< Event information required for binding cryptodev queue to
+ * eventdev queue. Used by crypto adapter.
+ */
+ uint8_t ca_enable;
+ /**< Set when queue pair is added to crypto adapter */
};
#endif /* _OTX2_CRYPTODEV_QP_H_ */
diff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
index 4a76d1d52..b47a7ad3e 100644
--- a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
+++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
@@ -1,3 +1,13 @@
DPDK_21 {
local: *;
};
+
+INTERNAL {
+ global:
+
+ otx2_ca_caps_get;
+ otx2_ca_qp_add;
+ otx2_ca_qp_del;
+
+ local: *;
+};
diff --git a/drivers/event/octeontx2/meson.build
b/drivers/event/octeontx2/meson.build
index 0ade51cec..8585c54e4 100644
--- a/drivers/event/octeontx2/meson.build
+++ b/drivers/event/octeontx2/meson.build
@@ -24,6 +24,6 @@ foreach flag: extra_flags
endif
endforeach
-deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2', 'pmd_octeontx2']
+deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2', 'pmd_octeontx2',
'pmd_octeontx2_crypto']
includes += include_directories('../../crypto/octeontx2')
diff --git a/drivers/event/octeontx2/otx2_evdev.c
b/drivers/event/octeontx2/otx2_evdev.c
index b8b57c388..fe21787b6 100644
--- a/drivers/event/octeontx2/otx2_evdev.c
+++ b/drivers/event/octeontx2/otx2_evdev.c
@@ -12,6 +12,7 @@
#include <rte_mbuf_pool_ops.h>
#include <rte_pci.h>
+#include "otx2_crypto_adapter.h"
#include "otx2_evdev_stats.h"
#include "otx2_evdev.h"
#include "otx2_irq.h"
@@ -1587,6 +1588,10 @@ static struct rte_eventdev_ops otx2_sso_ops = {
.timer_adapter_caps_get = otx2_tim_caps_get,
+ .crypto_adapter_caps_get = otx2_ca_caps_get,
+ .crypto_adapter_queue_pair_add = otx2_ca_qp_add,
+ .crypto_adapter_queue_pair_del = otx2_ca_qp_del,
+
.xstats_get = otx2_sso_xstats_get,
.xstats_reset = otx2_sso_xstats_reset,
.xstats_get_names = otx2_sso_xstats_get_names,
--
2.28.0
