On Fri, 4 Sep 2020 11:18:55 +0100 Liang Ma <liang.j...@intel.com> wrote:
> Add two new power management intrinsics, and provide an implementation > in eal/x86 based on UMONITOR/UMWAIT instructions. The instructions > are implemented as raw byte opcodes because there is not yet widespread > compiler support for these instructions. > > The power management instructions provide an architecture-specific > function to either wait until a specified TSC timestamp is reached, or > optionally wait until either a TSC timestamp is reached or a memory > location is written to. The monitor function also provides an optional > comparison, to avoid sleeping when the expected write has already > happened, and no more writes are expected. > > Signed-off-by: Liang Ma <liang.j...@intel.com> > Signed-off-by: Anatoly Burakov <anatoly.bura...@intel.com> This looks like a useful feature but needs more documentation and example. It would make sense to put an example in l3fwd-power.
