On 22 January 2015 at 14:29, Jay Rolette <rolette at infiniteio.com> wrote:
> Microseconds matter. Scaling up to 100GbE, nanoseconds matter. > True. Is there a cut-off point though? Does one nanosecond matter? AVX512 will fit a 64-byte packet in one register and move that to or from memory with one instruction. L1/L2 cache bandwidth per server is growing on a double-exponential curve (both bandwidth per core and cores per CPU). I wonder if moving data around in cache will soon be too cheap for us to justify worrying about. I suppose that 1500 byte wide registers are still a ways off though ;-) Cheers! -Luke (begging your indulgence for wandering off on a tangent)
