[dpdk-dev] [PATCH v3 01/27] net/e1000/base: i210 slow system clock update

[Guinan Sun]

This code is required for the update for system clock.

Signed-off-by: Todd Fujinaka <todd.fujin...@intel.com>
Signed-off-by: Guinan Sun <guinanx....@intel.com>
---
 drivers/net/e1000/base/e1000_i210.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/net/e1000/base/e1000_i210.c 
b/drivers/net/e1000/base/e1000_i210.c
index 9298223c3..d9cd1a084 100644
--- a/drivers/net/e1000/base/e1000_i210.c
+++ b/drivers/net/e1000/base/e1000_i210.c
@@ -900,6 +900,8 @@ STATIC s32 e1000_pll_workaround_i210(struct e1000_hw *hw)
        u16 nvm_word, phy_word, pci_word, tmp_nvm;
        int i;
 
+       /* Get PHY semaphore */
+       hw->phy.ops.acquire(hw);
        /* Get and set needed register values */
        wuc = E1000_READ_REG(hw, E1000_WUC);
        mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
@@ -915,8 +917,11 @@ STATIC s32 e1000_pll_workaround_i210(struct e1000_hw *hw)
        phy_word = E1000_PHY_PLL_UNCONF;
        for (i = 0; i < E1000_MAX_PLL_TRIES; i++) {
                /* check current state directly from internal PHY */
-               e1000_read_phy_reg_gs40g(hw, (E1000_PHY_PLL_FREQ_PAGE |
-                                        E1000_PHY_PLL_FREQ_REG), &phy_word);
+               e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, 0xFC);
+               usec_delay(20);
+               e1000_read_phy_reg_mdic(hw, E1000_PHY_PLL_FREQ_REG, &phy_word);
+               usec_delay(20);
+               e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, 0);
                if ((phy_word & E1000_PHY_PLL_UNCONF)
                    != E1000_PHY_PLL_UNCONF) {
                        ret_val = E1000_SUCCESS;
@@ -950,6 +955,8 @@ STATIC s32 e1000_pll_workaround_i210(struct e1000_hw *hw)
        }
        /* restore MDICNFG setting */
        E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
+       /* Release PHY semaphore */
+       hw->phy.ops.release(hw);
        return ret_val;
 }
 
-- 
2.17.1