[dpdk-dev] [PATCH v2 15/42] net/e1000/base: modify HW level time sync mechanisms

[Guinan Sun]

Add additinal configuration space access to allow HW
level time sync mechanism.

Signed-off-by: Efimov Evgeny <evgeny.efi...@intel.com>
Signed-off-by: Guinan Sun <guinanx....@intel.com>
---
 drivers/net/e1000/base/e1000_ich8lan.c | 18 ++++++++++++++++++
 drivers/net/e1000/base/e1000_ich8lan.h |  1 +
 2 files changed, 19 insertions(+)

diff --git a/drivers/net/e1000/base/e1000_ich8lan.c 
b/drivers/net/e1000/base/e1000_ich8lan.c
index 133cef4cd..4790196f2 100644
--- a/drivers/net/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/e1000/base/e1000_ich8lan.c
@@ -4894,6 +4894,7 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
        u16 kum_cfg;
        u32 ctrl, reg;
        s32 ret_val;
+       u16 pci_cfg;
 
        DEBUGFUNC("e1000_reset_hw_ich8lan");
 
@@ -4954,11 +4955,28 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
                        e1000_gate_hw_phy_config_ich8lan(hw, true);
        }
        ret_val = e1000_acquire_swflag_ich8lan(hw);
+
+       /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
+        * may occur during global reset and cause system hang.
+        * Configuration space access creates the needed delay.
+        * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
+        * insures configuration space read is done before global reset.
+        */
+       e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
+       E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
        DEBUGOUT("Issuing a global reset to ich8lan\n");
        E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
        /* cannot issue a flush here because it hangs the hardware */
        msec_delay(20);
 
+       /* Configuration space access improve HW level time sync mechanism.
+        * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
+        * value to insure configuration space read is done
+        * before any access to mac register.
+        */
+       e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
+       E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
+
        /* Set Phy Config Counter to 50msec */
        if (hw->mac.type == e1000_pch2lan) {
                reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
diff --git a/drivers/net/e1000/base/e1000_ich8lan.h 
b/drivers/net/e1000/base/e1000_ich8lan.h
index 9c21396c3..bfee467b3 100644
--- a/drivers/net/e1000/base/e1000_ich8lan.h
+++ b/drivers/net/e1000/base/e1000_ich8lan.h
@@ -287,6 +287,7 @@
 /* Receive Address Initial CRC Calculation */
 #define E1000_PCH_RAICC(_n)    (0x05F50 + ((_n) * 4))
 
+#define E1000_PCI_VENDOR_ID_REGISTER   0x00
 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 #define E1000_PCI_REVISION_ID_REG      0x08
 #endif /* defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) */
-- 
2.17.1