[dpdk-dev] [PATCH 58/70] net/e1000/base: add PHY power management control

[Guinan Sun]

PHY power management control should provide a reliable and accurate
indication of PHY reset completion and decrease the delay time
after a PHY reset.

Signed-off-by: Sasha Neftin <sasha.nef...@intel.com>
Signed-off-by: Guinan Sun <guinanx....@intel.com>
---
 drivers/net/e1000/base/e1000_defines.h |  4 ++++
 drivers/net/e1000/base/e1000_phy.c     | 12 +++++++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/net/e1000/base/e1000_defines.h 
b/drivers/net/e1000/base/e1000_defines.h
index 00afdaa25..effd04dfd 100644
--- a/drivers/net/e1000/base/e1000_defines.h
+++ b/drivers/net/e1000/base/e1000_defines.h
@@ -1100,8 +1100,12 @@
 #define ANEG_MULTIGBT_AN_CTRL  0x0020 /* MULTI GBT AN Control Register */
 #define MMD_DEVADDR_SHIFT      16     /* Shift MMD to higher bits */
 #define CR_2500T_FD_CAPS       0x0080 /* Advertise 2500T FD capability */
+
 #define PHY_CONTROL_LB         0x4000 /* PHY Loopback bit */
 
+
+#define E1000_PHY_RST_COMP     0x0100 /* Internal PHY reset completion */
+
 /* NVM Control */
 #define E1000_EECD_SK          0x00000001 /* NVM Clock */
 #define E1000_EECD_CS          0x00000002 /* NVM Chip Select */
diff --git a/drivers/net/e1000/base/e1000_phy.c 
b/drivers/net/e1000/base/e1000_phy.c
index b9d8739ee..712ec1269 100644
--- a/drivers/net/e1000/base/e1000_phy.c
+++ b/drivers/net/e1000/base/e1000_phy.c
@@ -2877,6 +2877,7 @@ s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
 {
        struct e1000_phy_info *phy = &hw->phy;
+       u32 phpm = 0, timeout = 10000;
        s32 ret_val;
        u32 ctrl;
 
@@ -2892,6 +2893,7 @@ s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
 
+       phpm = E1000_READ_REG(hw, E1000_I225_PHPM);
        ctrl = E1000_READ_REG(hw, E1000_CTRL);
        E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
        E1000_WRITE_FLUSH(hw);
@@ -2901,7 +2903,15 @@ s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
        E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
        E1000_WRITE_FLUSH(hw);
 
-       usec_delay(150);
+       /* SW should guarantee 100us for the completion of the PHY reset */
+       usec_delay(100);
+       do {
+               phpm = E1000_READ_REG(hw, E1000_I225_PHPM);
+               timeout--;
+               usec_delay(1);
+       } while (!(phpm & E1000_PHY_RST_COMP) && timeout);
+
+       usec_delay(100);
 
        phy->ops.release(hw);
 
-- 
2.17.1