On Wed, May 6, 2020 at 5:28 PM Phil Yang <phil.y...@arm.com> wrote: > > The rte_atomic ops and rte_smp barriers enforce DMB barriers on aarch64. > Using c11 atomics with explicit memory ordering instead of the rte_atomic > ops and rte_smp barriers for inter-threads synchronization can uplift the > performance on aarch64 and no performance loss on x86. > > This patchset contains: > 1) fix race condition for MT unsafe service. > 2) clean up redundant code. > 3) use c11 atomics for service core lib to avoid unnecessary barriers.
Series applied, thanks for the cleanup and fixes. -- David Marchand
