Hi > From: Xu, Rosen <rosen...@intel.com> > Hi, > > > -----Original Message----- > > From: Chautru, Nicolas <nicolas.chau...@intel.com> > > Sent: Tuesday, April 14, 2020 8:16 > > To: Xu, Rosen <rosen...@intel.com>; dev@dpdk.org; akhil.go...@nxp.com > > Cc: Richardson, Bruce <bruce.richard...@intel.com> > > Subject: RE: [dpdk-dev] [PATCH v2 06/13] baseband/fpga_5gnr_fec: add > > queue configuration > > > > Thanks Rosen for your thorough code review. Some comments in-line below. > > > > > From: Xu, Rosen <rosen...@intel.com> > > > > > > Hi, > > > > > > Could you prefix all functions name with the FPGA IP name? FPGA is a > > > very common device name. > > > > > > > I don't see such a guideline being used across all other PMDs. > > Unsure it always help notably as this would create many long function > > names with fpga_5gnr_fec_ added each time, and these names are not > > exposed outside of this .c file. > > Also some of the fpga_ prefixes would apply for either fpga_lte_fec or > > fpga_5gnr_fec PMD. > > If this becomes of a new guide lines we can rename every single > > function in each existing baseband PMD in future release (not just this new > PMD). > > What I mentioned is that, let's take FVL for example, in our PMD, we name it's > PMD functions with I40e_xxx, i40e is Intel NIC name, but for your design it > named with fpga_5gnr_xxx, fpga is a common device, That means not Intel > only provide FPGA, no sure if any other developer summit other FPGA based 5G > acceleration IP, is it ok? >
The new baseband PMD is indeed called "fpga_5gnr_fec" which may sound fairly generic. Note that that an older existing baseband PMD is currently called "fpga_lte_fec", the new PMD is the 5G version while the previous provided 4G capability. This depends on the user image being loaded onto the FPGA chip. Both these PMDs are in effect currently used by the ecosystem with the FPGA variant from Intel called Vista Creek (based on Altera Arria10 chip) but there is no limitation for same driver to be used on other chip (notably with increased cell density on newer process) as long as the HW ring interface is the same or compatible image is loaded agnostically on the chip. Let me know if unclear.
