This patch updates the MLX5 PMD and release notes documentations. Adding the notes of the behavior change that rte flows organization is switched into non-cached mode for applications.
Signed-off-by: Bing Zhao <bi...@mellanox.com> --- v2: update the description in release notes. --- doc/guides/nics/mlx5.rst | 10 ++++++++++ doc/guides/rel_notes/release_20_05.rst | 1 + 2 files changed, 11 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index e13c07d..63138c4 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -1287,6 +1287,16 @@ set, and we should allow to specify zero values as rte_flow parameters for the META and MARK items and actions. In the same time zero mask has no meaning and should be rejected on validation stage. +Notes for rte_flow +------------------ +Implementation of flows organization is in non-cached mode. When stopping a +device, all the flows inserted from application will be considered invalid and +flushed automatically in the background. After restarting of the device, no +application's flow exists in the system. + +The application should re-insert the flows as required after device restarting, +and must not try to destroy or flush the invalid flows before stopping. + Notes for testpmd ----------------- diff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst index 4b81893..b951745 100644 --- a/doc/guides/rel_notes/release_20_05.rst +++ b/doc/guides/rel_notes/release_20_05.rst @@ -62,6 +62,7 @@ New Features * Added support for matching on IPv4 Time To Live and IPv6 Hop Limit. * Added support for creating Relaxed Ordering Memory Regions. + * Flow rules caching removed from the driver for memory saving. * **Updated the Intel ice driver.** -- 1.8.3.1
