> -----Original Message-----
> From: Guo, Jia <jia....@intel.com>
> Sent: Saturday, April 11, 2020 8:10 AM
> To: Ye, Xiaolong <xiaolong...@intel.com>; Zhang, Qi Z <qi.z.zh...@intel.com>
> Cc: dev@dpdk.org; Wu, Jingjing <jingjing...@intel.com>; Cao, Yahui
> <yahui....@intel.com>; Su, Simei <simei...@intel.com>; Guo, Jia
> <jia....@intel.com>
> Subject: [dpdk-dev v3 1/4] ethdev: add new RSS offload types
> 
> Defines some new RSS offload types for ETH/SVLAN/CVLAN/GTPU/L2TPV3/
> ESP/AH/PFCP.
> 
> Signed-off-by: Jeff Guo <jia....@intel.com>
> ---
> v3->v2:
> 1.refine rss offload types.
> ---
> 
>  lib/librte_ethdev/rte_ethdev.h | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h
> index d1a593ad1..efe705ff0 100644
> --- a/lib/librte_ethdev/rte_ethdev.h
> +++ b/lib/librte_ethdev/rte_ethdev.h
> @@ -511,6 +511,13 @@ struct rte_eth_rss_conf {
>  #define ETH_RSS_GENEVE             (1ULL << 20)
>  #define ETH_RSS_NVGRE              (1ULL << 21)
>  #define ETH_RSS_GTPU               (1ULL << 23)
> +#define ETH_RSS_ETH             (1ULL << 24)
> +#define ETH_RSS_S_VLAN                  (1ULL << 25)
> +#define ETH_RSS_C_VLAN                  (1ULL << 26)
> +#define ETH_RSS_ESP             (1ULL << 27)
> +#define ETH_RSS_AH              (1ULL << 28)
> +#define ETH_RSS_L2TPV3                  (1ULL << 29)
> +#define ETH_RSS_PFCP            (1ULL << 30)
> 
>  /*
>   * We use the following macros to combine with above ETH_RSS_* for @@
> -524,7 +531,9 @@ struct rte_eth_rss_conf {
>  #define ETH_RSS_L3_SRC_ONLY        (1ULL << 63)
>  #define ETH_RSS_L3_DST_ONLY        (1ULL << 62)
>  #define ETH_RSS_L4_SRC_ONLY        (1ULL << 61)
> -#define ETH_RSS_L4_DST_ONLY        (1ULL << 60)
> +#define ETH_RSS_L4_DST_ONLY     (1ULL << 60)
> +#define ETH_RSS_ETH_SRC_ONLY    (1ULL << 59)
> +#define ETH_RSS_ETH_DST_ONLY    (1ULL << 58)
> 
>  /**
>   * For input set change of hash filter, if SRC_ONLY and DST_ONLY of
> --
> 2.20.1

Reviewed-by: Qi Zhang <qi.z.zh...@intel.com>


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