We nead isb rather than dsb to sync system counter to cntvct_el0. Signed-off-by: Haifeng Lin <haifeng....@huawei.com> --- lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++ lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++ 2 files changed, 5 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h index 859ae129d..705351394 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h @@ -21,6 +21,7 @@ extern "C" { #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define dmb(opt) asm volatile("dmb " #opt : : : "memory") +#define isb() asm volatile("isb" : : : "memory") #define rte_mb() dsb(sy) @@ -186,6 +187,8 @@ rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int128_t *exp, return (old.int128 == expected.int128); } +#define rte_isb() isb() + #ifdef __cplusplus } #endif diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h index 68e7c7338..29f524901 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h @@ -18,6 +18,7 @@ extern "C" { * The time base for this lcore. */ #ifndef RTE_ARM_EAL_RDTSC_USE_PMU + /** * This call is portable to any ARMv8 architecture, however, typically * cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks. @@ -27,6 +28,7 @@ rte_rdtsc(void) { uint64_t tsc; + rte_isb(); asm volatile("mrs %0, cntvct_el0" : "=r" (tsc)); return tsc; } -- 2.24.1.windows.2