On 2/20/2020 9:43 AM, Zhu, TaoX wrote:
> Hi Yigit, Ferruh
>
> The original author was not found. The meaning of these bits is as follows:
> ITR Index of the interrupt cause:
> 00b - ITR0 ; 01b - ITR1; 10b - ITR2; 11b - NoITR
>
> I think the reason why the original author wrote this strange code is to
> highlight that these bits are important in this function,
> he wanted to make it clear that he used ITR0 . I think it's possible, so I
> keep it.
That is OK, thanks for clarification.
>
>
> BR,
> Zhu, Tao
>
>
>> -----Original Message-----
>> From: Yigit, Ferruh
>> Sent: Thursday, February 20, 2020 5:21 PM
>> To: Zhu, TaoX <taox....@intel.com>; Yang, Qiming
>> <qiming.y...@intel.com>; Lu, Wenzhuo <wenzhuo...@intel.com>
>> Cc: dev@dpdk.org; Xing, Beilei <beilei.x...@intel.com>; Zhang, Qi Z
>> <qi.z.zh...@intel.com>; Ye, Xiaolong <xiaolong...@intel.com>;
>> sta...@dpdk.org
>> Subject: Re: [dpdk-dev] [PATCH] net/ice: fix queue bind MSI-X interrupt
>> error
>>
>> On 2/19/2020 10:17 AM, taox....@intel.com wrote:
>>> From: Zhu Tao <taox....@intel.com>
>>>
>>> To bind a queue to an MSI-X interrupt, need to set some register.
>>> The register consists of many parts, each of which has several bits;
>>> therefore, the shift operator '<<' was used; so the operator '<' in
>>> the code should be '<<'.
>>>
>>> Old code adds 1 on even MSI-X interrupt vector index used by queue,
>>> resulting in interrupt mapping error.
>>>
>>> Fixes: 65dfc889d8 ("net/ice: support Rx queue interruption")
>>> Cc: sta...@dpdk.org
>>>
>>> Signed-off-by: Zhu Tao <taox....@intel.com>
>>> ---
>>> drivers/net/ice/ice_ethdev.c | 4 ++--
>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/net/ice/ice_ethdev.c
>>> b/drivers/net/ice/ice_ethdev.c index 8e9369e0a..85ef83e92 100644
>>> --- a/drivers/net/ice/ice_ethdev.c
>>> +++ b/drivers/net/ice/ice_ethdev.c
>>> @@ -2605,9 +2605,9 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi,
>> uint16_t msix_vect,
>>> for (i = 0; i < nb_queue; i++) {
>>> /*do actual bind*/
>>> val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
>>> - (0 < QINT_RQCTL_ITR_INDX_S) |
>> QINT_RQCTL_CAUSE_ENA_M;
>>> + (0 << QINT_RQCTL_ITR_INDX_S) |
>> QINT_RQCTL_CAUSE_ENA_M;
>>> val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
>>> - (0 < QINT_TQCTL_ITR_INDX_S) |
>> QINT_TQCTL_CAUSE_ENA_M;
>>> + (0 << QINT_TQCTL_ITR_INDX_S) |
>> QINT_TQCTL_CAUSE_ENA_M;
>>
>> Hi Tao,
>>
>> Out of curiosity, what is the point of left shifting "0"?
