aarch64 does not map pci resources to 'write-combine' nor cacheable. In Linux Kernel arch_can_pci_mmap_wc() equals to 0 on aarch64[1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ tree/drivers/pci/pci-sysfs.c?h=v5.4#n1204 Fixes: f078ceb6ae93 ("net/mlx5: fix Tx doorbell write memory barrier") Cc: sta...@dpdk.org Signed-off-by: Gavin Hu <gavin...@arm.com> Reviewed-by: Phil Yang <phil.y...@arm.com> --- drivers/net/mlx5/mlx5_txq.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index bc13abfe6..144bab4a6 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -319,7 +319,11 @@ txq_uar_ncattr_init(struct mlx5_txq_ctrl *txq_ctrl, size_t page_size) off_t cmd; txq_ctrl->txq.db_heu = priv->config.dbnc == MLX5_TXDB_HEURISTIC; +#ifdef RTE_ARCH_ARM64 + txq_ctrl->txq.db_nc = 1; +#else txq_ctrl->txq.db_nc = 0; +#endif /* Check the doorbell register mapping type. */ cmd = txq_ctrl->uar_mmap_offset / page_size; cmd >>= MLX5_UAR_MMAP_CMD_SHIFT; -- 2.17.1
