> -----Original Message-----
> From: Li, Xiaoyun <xiaoyun...@intel.com>
> Sent: Wednesday, December 4, 2019 11:19 PM
> To: Wu, Jingjing <jingjing...@intel.com>
> Cc: dev@dpdk.org; Li, Xiaoyun <xiaoyun...@intel.com>; sta...@dpdk.org
> Subject: [PATCH] raw/ntb: fix write memory barrier issue
>
> All buffers and ring info should be written before tail register update.
> This patch relocates the write memory barrier before updating tail register
> to avoid potential issues.
>
> Fixes: 11b5c7daf019 ("raw/ntb: add enqueue and dequeue functions")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Xiaoyun Li <xiaoyun...@intel.com>
Acked-by: Jingjing Wu <jingjing...@intel.com>
