Armv8's peripheral coherence order is a total order on all reads and writes to that peripheral, that makes a compiler barrier is enough for abstracted rte io barrier.
For virtual PCI devices, the virtual device memory is actually normal memory and the Hypervisor view of things takes precedence and they are within a smp configuration and smp barriers should be used, the relaxed io barrier for aarch64 becomes insufficient. Gavin Hu (3): eal/arm64: relax the io barrier for aarch64 net/virtio: virtual PCI requires smp barriers crypto/virtio: virtual PCI requires smp barriers drivers/crypto/virtio/virtio_pci.c | 124 ++++++++++++++++----- drivers/net/virtio/virtio_pci.c | 124 ++++++++++++++++----- .../common/include/arch/arm/rte_atomic_64.h | 6 +- 3 files changed, 191 insertions(+), 63 deletions(-) -- 2.7.4
