The IPSec Multi buffer library does not require AES-NI
instructions to be supported by the CPU, as it can emulate these
instructions in software (adding a big performance penalty when
using AES algorithms).

Signed-off-by: Pablo de Lara <pablo.de.lara.gua...@intel.com>
---
v2:
- Fixed leading whitespaces

 drivers/crypto/aesni_gcm/aesni_gcm_pmd.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c 
b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
index 1006a5c..f029362 100644
--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
@@ -491,11 +491,6 @@ aesni_gcm_create(const char *name,
        enum aesni_gcm_vector_mode vector_mode;
        MB_MGR *mb_mgr;
 
-       /* Check CPU for support for AES instruction set */
-       if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES)) {
-               AESNI_GCM_LOG(ERR, "AES instructions not supported by CPU");
-               return -EFAULT;
-       }
        dev = rte_cryptodev_pmd_create(name, &vdev->device, init_params);
        if (dev == NULL) {
                AESNI_GCM_LOG(ERR, "driver %s: create failed",
@@ -522,10 +517,15 @@ aesni_gcm_create(const char *name,
 
        dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
                        RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
-                       RTE_CRYPTODEV_FF_CPU_AESNI |
                        RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
                        RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT;
 
+       /* Check CPU for support for AES instruction set */
+       if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES))
+               dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AESNI;
+       else
+               AESNI_GCM_LOG(WARNING, "AES instructions not supported by CPU");
+
        mb_mgr = alloc_mb_mgr(0);
        if (mb_mgr == NULL)
                return -ENOMEM;
-- 
2.7.5

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