On Wed, Oct 9, 2019 at 1:15 PM Jakub Grajciar -X (jgrajcia - PANTHEON TECHNOLOGIES at Cisco) <jgraj...@cisco.com> wrote: > > > > > -----Original Message----- > > From: Phil Yang <phil.y...@arm.com> > > Sent: Wednesday, October 9, 2019 4:05 AM > > To: Jakub Grajciar -X (jgrajcia - PANTHEON TECHNOLOGIES at Cisco) > > <jgraj...@cisco.com>; ferruh.yi...@intel.com; dev@dpdk.org > > Cc: tho...@monjalon.net; Damjan Marion (damarion) > > <damar...@cisco.com>; honnappa.nagaraha...@arm.com; > > gavin...@arm.com; n...@arm.com > > Subject: [PATCH v2] net/memif: optimized with one-way barrier > > > > Using 'rte_mb' to synchronize the shared ring head/tail between producer and > > consumer will stall the pipeline and damage performance on the weak > > memory model platform such like AArch64. Meanwhile update the shared > > ring head and tail are observable and ordered between CPUs on IA. > > > > Optimized this full barrier with the one-way barrier can improve the > > throughput. On AArch64 n1sdp server this patch make testpmd throughput > > boost 2.1%. On Intel E5-2640, testpmd got 3.98% performance gain. > > > > Signed-off-by: Phil Yang <phil.y...@arm.com> > > Reviewed-by: Gavin Hu <gavin...@arm.com> > > --- > > v2: > > Upgrade 'MEMIF_VERSION_MAJOR' number to 3. (Jakub Grajciar) > > > > v1: > > Initial version. > > I jumped the gun with the version bump. The change doesn't break > compatibility. I'm putting reviewed label on v1. > > Sorry for the inconvenience.
Ok, marking v2 as rejected then. -- David Marchand
