This patch reserves several bits as input set selection from the
high end of the 64 bits. It is combined with exisiting ETH_RSS_*
to represent RSS types.
Signed-off-by: Simei Su <simei...@intel.com>
Reviewed-by: Qi Zhang <qi.z.zh...@intel.com>
Acked-by: Ori Kam <or...@mellanox.com>
---
lib/librte_ethdev/rte_ethdev.c | 42 ++++++++++++++++++++++++++++++++++++++++++
lib/librte_ethdev/rte_ethdev.h | 14 ++++++++++++++
2 files changed, 56 insertions(+)
diff --git a/lib/librte_ethdev/rte_ethdev.c b/lib/librte_ethdev/rte_ethdev.c
index af82360..1666652 100644
--- a/lib/librte_ethdev/rte_ethdev.c
+++ b/lib/librte_ethdev/rte_ethdev.c
@@ -1115,6 +1115,26 @@ struct rte_eth_dev *
return name;
}
+static uint64_t
+strip_out_src_dst_only(uint64_t value, uint64_t layer)
+{
+ uint64_t flag = 0;
+
+ if (layer == 3) {
+ if ((value & ETH_RSS_L3_SRC_ONLY) &&
+ (value & ETH_RSS_L3_DST_ONLY))
+ flag = 1;
+ }
+
+ if (layer == 4) {
+ if ((value & ETH_RSS_L4_SRC_ONLY) &&
+ (value & ETH_RSS_L4_DST_ONLY))
+ flag = 1;
+ }
+
+ return flag;
+}
+
int
rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q,
const struct rte_eth_conf *dev_conf)
@@ -1124,6 +1144,8 @@ struct rte_eth_dev *
struct rte_eth_conf orig_conf;
int diag;
int ret;
+ uint64_t layer3 = 3;
+ uint64_t layer4 = 4;
RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
@@ -1269,6 +1291,16 @@ struct rte_eth_dev *
goto rollback;
}
+ if (strip_out_src_dst_only(
+ dev_conf->rx_adv_conf.rss_conf.rss_hf, layer3) == 1)
+ dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf &=
+ ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY);
+
+ if (strip_out_src_dst_only(
+ dev_conf->rx_adv_conf.rss_conf.rss_hf, layer4) == 1)
+ dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf &=
+ ~(ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
+
/* Check that device supports requested rss hash functions. */
if ((dev_info.flow_type_rss_offloads |
dev_conf->rx_adv_conf.rss_conf.rss_hf) !=
@@ -3105,6 +3137,8 @@ struct rte_eth_dev *
struct rte_eth_dev *dev;
struct rte_eth_dev_info dev_info = { .flow_type_rss_offloads = 0, };
int ret;
+ uint64_t layer3 = 3;
+ uint64_t layer4 = 4;
RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
@@ -3112,6 +3146,14 @@ struct rte_eth_dev *
if (ret != 0)
return ret;
+ if (strip_out_src_dst_only(rss_conf->rss_hf, layer3) == 1)
+ rss_conf->rss_hf &=
+ ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY);
+
+ if (strip_out_src_dst_only(rss_conf->rss_hf, layer4) == 1)
+ rss_conf->rss_hf &=
+ ~(ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
+
dev = &rte_eth_devices[port_id];
if ((dev_info.flow_type_rss_offloads | rss_conf->rss_hf) !=
dev_info.flow_type_rss_offloads) {
diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h
index 7722f70..6d61b84 100644
--- a/lib/librte_ethdev/rte_ethdev.h
+++ b/lib/librte_ethdev/rte_ethdev.h
@@ -505,6 +505,20 @@ struct rte_eth_rss_conf {
#define ETH_RSS_GENEVE (1ULL << 20)
#define ETH_RSS_NVGRE (1ULL << 21)
+/*
+ * We use the following macros to combine with above ETH_RSS_* for
+ * more specific input set selection. These bits are defined starting
+ * from the high end of the 64 bits.
+ * Note: If we use above ETH_RSS_* without SRC/DST_ONLY, it represents
+ * both SRC and DST are taken into account. If SRC_ONLY and DST_ONLY of
+ * the same level be used simultaneously, it is the same case as none of
+ * them are added.
+ */
+#define ETH_RSS_L3_SRC_ONLY (1ULL << 63)
+#define ETH_RSS_L3_DST_ONLY (1ULL << 62)
+#define ETH_RSS_L4_SRC_ONLY (1ULL << 61)
+#define ETH_RSS_L4_DST_ONLY (1ULL << 60)
+
#define ETH_RSS_IP ( \
ETH_RSS_IPV4 | \
ETH_RSS_FRAG_IPV4 | \
--
1.8.3.1
