> -----Original Message----- > From: Phil Yang (Arm Technology China) <phil.y...@arm.com> > Sent: Wednesday, August 14, 2019 3:55 PM > To: Jerin Jacob Kollanukkaran <jer...@marvell.com>; tho...@monjalon.net; > gage.e...@intel.com; dev@dpdk.org > Cc: hemant.agra...@nxp.com; Honnappa Nagarahalli > <honnappa.nagaraha...@arm.com>; Gavin Hu (Arm Technology China) > <gavin...@arm.com>; nd <n...@arm.com>; nd <n...@arm.com> > Subject: [EXT] RE: [PATCH v9 1/3] eal/arm64: add 128-bit atomic compare > exchange > > External Email > > ---------------------------------------------------------------------- > > -----Original Message----- > > From: Jerin Jacob Kollanukkaran <jer...@marvell.com> > > Sent: Wednesday, August 14, 2019 4:46 PM > > To: Phil Yang (Arm Technology China) <phil.y...@arm.com>; > > tho...@monjalon.net; gage.e...@intel.com; dev@dpdk.org > > Cc: hemant.agra...@nxp.com; Honnappa Nagarahalli > > <honnappa.nagaraha...@arm.com>; Gavin Hu (Arm Technology China) > > <gavin...@arm.com>; nd <n...@arm.com> > > Subject: RE: [PATCH v9 1/3] eal/arm64: add 128-bit atomic compare > > exchange > > > > > -----Original Message----- > > > From: Phil Yang <phil.y...@arm.com> > > > Sent: Wednesday, August 14, 2019 1:58 PM > > > To: tho...@monjalon.net; Jerin Jacob Kollanukkaran > > <jer...@marvell.com>; > > > gage.e...@intel.com; dev@dpdk.org > > > Cc: hemant.agra...@nxp.com; honnappa.nagaraha...@arm.com; > > > gavin...@arm.com; n...@arm.com > > > Subject: [EXT] [PATCH v9 1/3] eal/arm64: add 128-bit atomic compare > > > exchange > > > +#define __HAS_ACQ(mo) ((mo) != __ATOMIC_RELAXED && (mo) != > > > +__ATOMIC_RELEASE) #define __HAS_RLS(mo) ((mo) == > > > __ATOMIC_RELEASE || (mo) == __ATOMIC_ACQ_REL || \ > > > + (mo) == __ATOMIC_SEQ_CST) > > > + > > > +#define __MO_LOAD(mo) (__HAS_ACQ((mo)) ? __ATOMIC_ACQUIRE : > > > +__ATOMIC_RELAXED) #define __MO_STORE(mo) (__HAS_RLS((mo)) ? > > > +__ATOMIC_RELEASE : __ATOMIC_RELAXED) > > > + > > > +#if defined(__ARM_FEATURE_ATOMICS) || > > > defined(RTE_ARM_FEATURE_ATOMICS) > > > +#define __ATOMIC128_CAS_OP(cas_op_name, op_string) > \ > > > +static __rte_noinline rte_int128_t > > > \ > > > > > > Could you check the cost of making it as __rte_noinline? > > If it is costly, How about having two versions, one with > > __rte_noinline to make compliance with arm64 procedure call standard > > for old gcc and clang. > > Other one without explicit register hardcoding + inline for latest gcc > > Hi Jerin,
Hi Phil Yang, > According to the stack_lf_perf_autotest, making it as __rte_noinline has no > overhead on ThunderX2 with GCC 8.3. > The 'Average cycles per object push/pop' numbers for __rte_noinline and > __rte_always_inline versions are nearly the same. I tested with octeontx2 as well. It is yielding similar result. No change is expected in this patch then.
