26/07/2019 07:24, jer...@marvell.com:
> From: Jerin Jacob <jer...@marvell.com>
>
> OTX2 AP core can sometimes fissure STP instructions when it is more
> optimal to send such writes into the pipeline as 2 separate
> instructions. However registers should be excluded from such
> optimization. This commit ensures that no CSR write is ever fissured
> by introducing zero cost workaround by setting STP pre-index by zero to
> make sure OTX2 AP core prevent fissure.
>
> Fixes: 8a4f835971f5 ("common/octeontx2: add IO handling APIs")
>
> Signed-off-by: Jerin Jacob <jer...@marvell.com>
Applied, thanks
