Hi Phil, Looks good overall, just a few documentation issues.
<snip> > + * > + * - Test "128b compare and swap" (aarch64 and x86_64 only) > + * > + * - Initialize 128-bit atomic variables to zero. > + * > + * - Invoke ``test_atomici128_cmp_exchange()`` on each lcore. Before > doing > + * anything else, the cores are waiting a synchro. Each lcore does > + * these compare and swap (CAS) operations several times:: > + * > + * Relaxed CAS update counter.val[0] + 2; counter.val[0] + 1; > + * Acquired CAS update counter.val[0] + 2; counter.val[0] + 1; > + * Released CAS update counter.val[0] + 2; counter.val[0] + 1; > + * Acquired_Released CAS update counter.val[0] + 2; counter.val[0] + 1; The array index in "counter.val[0] + 1", is incorrect, I believe. Just a nitpick, but "Relaxed CAS update" can go last to match the order in the code. <snip> > +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64) > +/* > + * rte_atomic128_cmp_exchange() should update a 128 bits counter's > +first 64 > + * bits by 2 and the second 64 bits by 1 in this test. It should return > +true > + * if the compare exchange operation successful. "operation successful" -> "operation is successful" > + * This test repeat 128 bits compare and swap operations 10K rounds. In > +each "repeat" -> "repeats" Thanks, Gage
