Hi Shreyansh, > -----Original Message----- > From: Shreyansh Jain <shreyansh.j...@nxp.com> > Sent: Monday, April 15, 2019 14:48 > To: Ruifeng Wang (Arm Technology China) <ruifeng.w...@arm.com>; > Ananyev, Konstantin <konstantin.anan...@intel.com>; dev@dpdk.org > Cc: nd <n...@arm.com>; nd <n...@arm.com> > Subject: RE: [dpdk-dev] [PATCH] examples/l3fwd: support separate buffer > pool per port > > Hi Ruifeng, > > [...] > > > > > > > For hardware backed pools, hardware access and exclusion are > > expensive. By > > > segregating pool/port/lcores it is possible to attain a conflict free > > path. This is > > > the use-case this patch targets. > > > And anyways, this is an optional feature. > > > > > > > Konstantin > > > > > > > > > In dual core test, both modes had nearly same performance. > > > > > > OK > > > > > > > > > > > > > My setup only has two ports which is limited. > > > > > Just want to know the per-port-pool mode has more performance > gain > > > > when many ports are bound to different cores? > > > > > > Yes, though not necessarily *many* - in my case, I had 4 ports and > > even then > > > about ~10% improvement was directly visible. I increased the port > > count and > > > I was able to touch about ~15%. I did pin each port to a separate > > core, though. > > > But again, important point is that without this feature enabled, I > > didn't see > > > any drop in performance. Did you observe any drop? > > > > > > > No, no drop without the feature enabled in my test. > > So, in case this is an optional feature, it should be fine, right? > (Obviously, assuming that my logical implementation is correct) > > At my end also, I saw no drop in performance without this feature (Default) > and a decent increase with this (with separate port-core combination) on > NXP platform. > > [...]
Tested on LS2088A and observed 12% performance gain when 4 ports were used. I think sample_app_ug document should be updated to add the new option. Acked-by: Ruifeng Wang <ruifeng.w...@arm.com> Regards, /Ruifeng
