Per the email discussion [1], the default cache line size of armv8 cortex-a72 is changed to 64 bytes.
[1] https://mails.dpdk.org/archives/dev/2019-January/123218.html Signed-off-by: Yongseok Koh <ys...@mellanox.com> --- config/arm/meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index e00b894523..73c581948c 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -51,6 +51,8 @@ flags_dpaa2 = [ ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] flags_default_extra = [] +flags_cortex_a72_extra = [ + ['RTE_CACHE_LINE_SIZE', 64]] flags_thunderx_extra = [ ['RTE_MACHINE', '"thunderx"'], ['RTE_USE_C11_MEM_MODEL', false]] @@ -73,7 +75,7 @@ machine_args_generic = [ ['0xd03', ['-mcpu=cortex-a53']], ['0xd04', ['-mcpu=cortex-a35']], ['0xd07', ['-mcpu=cortex-a57']], - ['0xd08', ['-mcpu=cortex-a72']], + ['0xd08', ['-mcpu=cortex-a72'], flags_cortex_a72_extra], ['0xd09', ['-mcpu=cortex-a73']], ['0xd0a', ['-mcpu=cortex-a75']]] -- 2.21.0.196.g041f5ea
