On 4/10/2019 12:13 AM, Yongseok Koh wrote:
> UAR (User Access Region) register does not need to be remapped for primary
> process but it should be remapped only for secondary process. UAR register
> table is in the process private structure in rte_eth_devices[],
> (struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private
>
> The actual UAR table follows the data structure and the table is used for
> both Tx and Rx.
>
> For Tx, BlueFlame in UAR is used to ring the doorbell. MLX5_TX_BFREG(txq)
> is defined to get a register for the txq. Processes access its own private
> data to acquire the register from the UAR table.
>
> For Rx, the doorbell in UAR is required in arming CQ event. However, it is
> a known issue that the register isn't remapped for secondary process.
>
> Signed-off-by: Yongseok Koh <ys...@mellanox.com>
<...>
> @@ -229,13 +229,99 @@ mlx5_tx_queue_release(void *dpdk_txq)
> }
> }
>
> +/**
> + * Initialize Tx UAR registers for primary process.
> + *
> + * @param txq_ctrl
> + * Pointer to Tx queue control structure.
> + */
> +static void
> +txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
> +{
> + struct mlx5_priv *priv = txq_ctrl->priv;
> + struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
> +
> + assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
> + assert(ppriv);
> + ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
> +#ifndef RTE_ARCH_64
> + struct mlx5_priv *priv = txq_ctrl->priv;
> + struct mlx5_txq_data *txq = &txq_ctrl->txq;
> + unsigned int lock_idx;
> + /* Assign an UAR lock according to UAR page number */
> + lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
> + MLX5_UAR_PAGE_NUM_MASK;
> + txq->uar_lock = &priv->uar_lock[lock_idx];
> +#endif
> +}
This won't compile for arch is not 64bits, since 'page_size' in that block is
not defined.
