Thursday, March 21, 2019 4:12 PM, Slava Ovsiienko:
> Subject: RE: [PATCH 14/14] net/mlx5: add source vport match to the ingress
> rules
> > >
> > > Signed-off-by: Viacheslav Ovsiienko <viachesl...@mellanox.com>
[...]
> > > + flow_dv_translate_source_vport(matcher.mask.buf,
> > > + dev_flow->dv.value.buf,
> > > + priv->representor_id < 0 ?
> > > + priv->representor_id :
> > > + priv->representor_id + 1,
> >
> > The vport of representor_id 0 will be 1?
> > Who owns vport 0?
>
> PF.
> There is the foillowing vport mapping (for single E-Switch per PF):
>
> -1 - wire
Wire, i.e. the uplink representor. indeed it's index is defined by PRM to -1.
> 0 - PF (uplink + VF reps)
I don't understand this part. When you have uplink representor you don't have
PF.
Moreover, I would expect the first representor created to have vport_num=0 (w/
name pf0vf0).
Isn't it the case?
> 1 - VF0
> 2 - VF1
> ...
> n+1 - VFn
>
> This code is subject to change - (SF, multi E-Switch per function, etc), this
> patch currently supports single E-Switch per PF.
>
> >
> > > + 0xffff);
> > > + }
> > > for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
> > > int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
> > > void *match_mask = matcher.mask.buf;
> > > --
> > > 1.8.3.1
