This patch addresses x86-64 only; other architectures can/will be supported in the future. The __atomic intrinsic was considered for the implementation, however libatomic was found[1] to use locks to implement the 128-bit CAS on at least one architecture and so is eschewed here. The interface is modeled after the __atomic_compare_exchange_16 (which itself is based on the C++11 memory model) to best support weak consistency architectures.
This patch was originally part of a series that introduces a non-blocking stack mempool handler[2], and is required by a non-blocking ring patchset. This patch was spun off so that the the NB ring depends only on this patch and not on the entire non-blocking stack patchset. [1] http://mails.dpdk.org/archives/dev/2019-January/124002.html [2] http://mails.dpdk.org/archives/dev/2019-January/123653.html v3: - Rename function to ISA-neutral rte_atomic128_cmp_exchange() - Fix two pseudocode bugs in function documentation v2: - Rename function to rte_atomic128_cmpxchg() - Replace "=A" output constraint with "=a" and "=d" to prevent GCC from using the al register for the sete destination - Extend 'weak' definition to allow non-atomic 'exp' updates. - Add const keyword to 'src' and remove volatile keyword from 'dst' - Put __int128 in a union in rte_int128_t and move the structure definition inside the RTE_ARCH_x86_64 ifdef - Drop enum rte_atomic_memmodel_t in favor of compiler-defined __ATOMIC_* - Drop unnecessary comment relating to X86_64 - Tweak the pseudocode to reflect the 'exp' update on failure. Gage Eads (1): eal: add 128-bit compare exchange (x86-64 only) .../common/include/arch/x86/rte_atomic_64.h | 33 ++++++++++++ lib/librte_eal/common/include/generic/rte_atomic.h | 59 ++++++++++++++++++++++ 2 files changed, 92 insertions(+) -- 2.13.6
