> Subject: [dpdk-dev] [PATCH v3 1/2] eal: add 128-bit cmpset (x86-64 only)
>
> This operation can be used for non-blocking algorithms, such as a non-
> blocking stack or ring.
>
> Signed-off-by: Gage Eads <gage.e...@intel.com>
> ---
> .../common/include/arch/x86/rte_atomic_64.h | 22
> ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h
> b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h
> index fd2ec9c53..34c2addf8 100644
> --- a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h
> +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h
Since this is a 128b operation should there be a new file created with the name
rte_atomic_128.h?
> @@ -34,6 +34,7 @@
> /*
> * Inspired from FreeBSD src/sys/amd64/include/atomic.h
> * Copyright (c) 1998 Doug Rabson
> + * Copyright (c) 2019 Intel Corporation
> * All rights reserved.
> */
>
> @@ -208,4 +209,25 @@ static inline void rte_atomic64_clear(rte_atomic64_t
> *v) } #endif
>
> +static inline int
> +rte_atomic128_cmpset(volatile uint64_t *dst, uint64_t *exp, uint64_t
> +*src) {
The API name suggests it is a 128b operation. 'dst', 'exp' and 'src' should be
pointers to 128b (__int128)? Or we could define our own data type.
Since, it is a new API, can we define it with memory orderings which will be
more conducive to relaxed memory ordering based architectures? You can refer to
[1] and [2] for guidance.
If this an external API, it requires 'experimental' tag.
1.
https://github.com/ARM-software/progress64/blob/master/src/lockfree/aarch64.h#L63
2.
https://github.com/ARM-software/progress64/blob/master/src/lockfree/x86-64.h#L34
> + uint8_t res;
> +
> + asm volatile (
> + MPLOCKED
> + "cmpxchg16b %[dst];"
> + " sete %[res]"
> + : [dst] "=m" (*dst),
> + [res] "=r" (res)
> + : "c" (src[1]),
> + "b" (src[0]),
> + "m" (*dst),
> + "d" (exp[1]),
> + "a" (exp[0])
> + : "memory");
> +
> + return res;
> +}
> +
> #endif /* _RTE_ATOMIC_X86_64_H_ */
> --
> 2.13.6
