> > > > I doubt it is possible to benchmark with such a precision so to see the > > potential difference of one ADD instruction. > > Just changes in function alignment can affect performance by percents. > And > > the natural variation when not using a 100% deterministic system is > going > to > > be a lot larger than one cycle per ring buffer operation. > > > > Some of the other patches are also for correctness (e.g. load-acquire of > tail) > The discussion is about this patch alone. Other patches are already Acked. > So the benchmarking then makes zero sense. The whole point is to prove the effect of 1 instruction either way. IMO, it is simple enough, follow the memory model to the full extent. We have to keep in mind about other architectures as well. May be that additional instruction is not required on other architectures.
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