Request management FW for OEM values, which are negotiated prior to the driver load by sending the GET_OEM_UPDATES command after both engines are initialized.
Signed-off-by: Rasesh Mody <rasesh.m...@cavium.com> --- drivers/net/qede/base/ecore_dev.c | 14 ++++++++++++++ drivers/net/qede/base/mcp_public.h | 8 ++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c index f0adf18..30e12e9 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -2646,6 +2646,20 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, } if (IS_PF(p_dev)) { + /* Get pre-negotiated values for stag, bandwidth etc. */ + p_hwfn = ECORE_LEADING_HWFN(p_dev); + DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, + "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n"); + rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, + DRV_MSG_CODE_GET_OEM_UPDATES, + 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET, + &resp, ¶m); + if (rc != ECORE_SUCCESS) + DP_NOTICE(p_hwfn, false, + "Failed to send GET_OEM_UPDATES attention request\n"); + } + + if (IS_PF(p_dev)) { p_hwfn = ECORE_LEADING_HWFN(p_dev); drv_mb_param = STORM_FW_VERSION; rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h index 2ee8ab5..46ec984 100644 --- a/drivers/net/qede/base/mcp_public.h +++ b/drivers/net/qede/base/mcp_public.h @@ -1696,6 +1696,8 @@ struct public_drv_mb { #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000 +#define FW_MSG_CODE_GET_OEM_UPDATES_DONE 0x41000000 + #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 @@ -1804,6 +1806,12 @@ struct public_drv_mb { #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0) +#define FW_MB_PARAM_OEM_UPDATE_MASK 0xFF +#define FW_MB_PARAM_OEM_UPDATE_OFFSET 0 +#define FW_MB_PARAM_OEM_UPDATE_BW 0x01 +#define FW_MB_PARAM_OEM_UPDATE_S_TAG 0x02 +#define FW_MB_PARAM_OEM_UPDATE_CFG 0x04 + u32 drv_pulse_mb; #define DRV_PULSE_SEQ_MASK 0x00007fff #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 -- 1.7.10.3