This patch introduces necessary changes required by MUSDK 18.09 library.
* As of MUSDK 18.09, pp2_cookie_t is no longer available. Now
RX descriptor cookie is defined as plain u64 so existing cast
is no longer valid.
* MUSDK 18.09 increased number of available bpools (buffer hw pools) by
introducing dma regions support. Update mvpp2 driver accordingly.
* replace MV_NET_IP4_F_TOS with MV_NET_IP4_F_DSCP
Before this patch, API allowed to configure a classification rule
according to IPv4 TOS, which was not supported in classifier. This patch
fixes this by using proper field.
* use 48 bit address mask
We cannot get pointers exceeding 48 bits thus using 48 bit
mask for extracting higher IOVA address bits is enough.
Signed-off-by: Natalie Samsonov <nsams...@marvell.com>
Signed-off-by: Yuval Caduri <cyu...@marvell.com>
Signed-off-by: Tomasz Duszynski <t...@semihalf.com>
Reviewed-by: Shlomi Gridish <sgrid...@marvell.com>
Reviewed-by: Alan Winkowski <wa...@marvell.com>
Reviewed-by: Liron Himi <lir...@marvell.com>
---
drivers/net/mvpp2/mrvl_ethdev.c | 10 ++++------
drivers/net/mvpp2/mrvl_flow.c | 3 ++-
drivers/net/mvpp2/mrvl_qos.c | 2 +-
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c
index 035ee81..899a9e4 100644
--- a/drivers/net/mvpp2/mrvl_ethdev.c
+++ b/drivers/net/mvpp2/mrvl_ethdev.c
@@ -54,9 +54,7 @@
#define MRVL_ARP_LENGTH 28
#define MRVL_COOKIE_ADDR_INVALID ~0ULL
-
-#define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
-#define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
+#define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000
/** Port Rx offload capabilities */
#define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
@@ -1544,7 +1542,7 @@ mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
entries[i].buff.addr =
rte_mbuf_data_iova_default(mbufs[i]);
- entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
+ entries[i].buff.cookie = (uint64_t)mbufs[i];
entries[i].bpool = bpool;
}
@@ -2180,7 +2178,7 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts,
uint16_t nb_pkts)
if (unlikely(status != PP2_DESC_ERR_OK)) {
struct pp2_buff_inf binf = {
.addr = rte_mbuf_data_iova_default(mbuf),
- .cookie = (pp2_cookie_t)(uint64_t)mbuf,
+ .cookie = (uint64_t)mbuf,
};
pp2_bpool_put_buff(hif, bpool, &binf);
@@ -2441,7 +2439,7 @@ mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts)
rte_mbuf_prefetch_part2(pref_pkt_hdr);
}
- sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
+ sq->ent[sq->head].buff.cookie = (uint64_t)mbuf;
sq->ent[sq->head].buff.addr =
rte_mbuf_data_iova_default(mbuf);
sq->ent[sq->head].bpool =
diff --git a/drivers/net/mvpp2/mrvl_flow.c b/drivers/net/mvpp2/mrvl_flow.c
index 065b1aa..ffd1dab 100644
--- a/drivers/net/mvpp2/mrvl_flow.c
+++ b/drivers/net/mvpp2/mrvl_flow.c
@@ -2437,7 +2437,8 @@ mrvl_create_cls_table(struct rte_eth_dev *dev, struct
rte_flow *first_flow)
if (first_flow->pattern & F_IP4_TOS) {
key->proto_field[key->num_fields].proto = MV_NET_PROTO_IP4;
- key->proto_field[key->num_fields].field.ipv4 = MV_NET_IP4_F_TOS;
+ key->proto_field[key->num_fields].field.ipv4 =
+ MV_NET_IP4_F_DSCP;
key->key_size += 1;
key->num_fields += 1;
}
diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c
index 5d80c3e..7fd9703 100644
--- a/drivers/net/mvpp2/mrvl_qos.c
+++ b/drivers/net/mvpp2/mrvl_qos.c
@@ -654,7 +654,7 @@ setup_tc(struct pp2_ppio_tc_params *param, uint8_t inqs,
struct pp2_ppio_inq_params *inq_params;
param->pkt_offset = MRVL_PKT_OFFS;
- param->pools[0] = bpool;
+ param->pools[0][0] = bpool;
param->default_color = color;
inq_params = rte_zmalloc_socket("inq_params",
--
2.7.4
