17/07/2018 15:31, Pablo de Lara:
> When non consecutive cores are passed into the test application,
> the distribution of the keys that each thread needs to insert
> is not correct, since it assumes that there are no cores skipped
> between the master core and the worker core.
>
> Fixes: be856325cba3 ("hash: add scalable multi-writer insertion with Intel
> TSX")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Pablo de Lara <pablo.de.lara.gua...@intel.com>Series applied, thanks
