> -----Original Message-----
> From: Wang, Yipeng1
> Sent: Friday, July 6, 2018 8:47 PM
> To: De Lara Guarch, Pablo <pablo.de.lara.gua...@intel.com>
> Cc: dev@dpdk.org; Wang, Yipeng1 <yipeng1.w...@intel.com>; Richardson,
> Bruce <bruce.richard...@intel.com>; honnappa.nagaraha...@arm.com;
> vgu...@caviumnetworks.com; brijesh.s.si...@gmail.com
> Subject: [PATCH v3 1/8] hash: fix multiwriter lock memory allocation
> 
> When malloc for multiwriter_lock, the align should be RTE_CACHE_LINE_SIZE
> rather than LCORE_CACHE_SIZE.
> 
> Also there should be check to verify the success of rte_malloc.
> 
> Fixes: be856325cba3 ("hash: add scalable multi-writer insertion with Intel 
> TSX")
> Cc: sta...@dpdk.org
> 
> Signed-off-by: Yipeng Wang <yipeng1.w...@intel.com>

Acked-by: Pablo de Lara <pablo.de.lara.gua...@intel.com>

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