On Fri, Jul 06, 2018 at 09:04:44AM +0200, Maxime Coquelin wrote: > This series is again preliminray work to ease packed ring > layout integration. > > Main changes are using vector buffres also in the dequeue > path, and perform IOVA to HVA translation at vectors fill > time. > > I still have to run more benchmarks, but PVP benchmarks does > not show performance changes. > > Good thing is that it saves ~140 further lines. > > Changes since v3: > ================= > - Fix dequeue_zero_copy last_used_idx update (Tiwei) > - Remove "vhost: make gpa to hpa failure an error" patch (Tiwei) > > Changes since v2: > ================= > - check vec_id doesn't overflow (Tiwei) > - Fix perm parameters passed to fill_vec_buf (Tiwei) > - Remove extra space in variable assignation (Tiwei) > > > Maxime Coquelin (5): > vhost: use shadow used ring in dequeue path > vhost: use buffer vectors in dequeue path > vhost: improve prefetching in dequeue path > vhost: prefetch first descriptor in dequeue path > vhost: improve prefetching in enqueue path > > lib/librte_vhost/vhost.h | 1 + > lib/librte_vhost/virtio_net.c | 517 > ++++++++++++++++-------------------------- > 2 files changed, 193 insertions(+), 325 deletions(-) > > -- > 2.14.4 >
For the series: Acked-by: Tiwei Bie <tiwei....@intel.com>
