Signed-off-by: Shreyansh Jain <shreyansh.j...@nxp.com>
---
note: pattern of this doc change is different from other NICs as NXP
SoC have integrated NICs. Thus, separating CPU from NIC doesn't make
much sense.
doc/guides/rel_notes/release_18_05.rst | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/doc/guides/rel_notes/release_18_05.rst
b/doc/guides/rel_notes/release_18_05.rst
index a7908828e..1ba4b9e1e 100644
--- a/doc/guides/rel_notes/release_18_05.rst
+++ b/doc/guides/rel_notes/release_18_05.rst
@@ -828,3 +828,14 @@ Tested Platforms
* Host interface: PCI Express 3.0 x16
* Device ID: 15b3:1017
* Firmware version: 16.22.0428
+
+* ARM SoC combinations from NXP (with integrated NICs)
+
+ * SoC:
+
+ * NXP/Freescale QorIQ LS1046A with ARM Cortex A72
+ * NXP/Freescale QorIQ LS2088A with ARM Cortex A72
+
+ * OS:
+
+ * Ubuntu 16.04.3 LTS with NXP QorIQ LSDK 1803 support packages
--
2.17.0
