On Wed, Nov 05, 2014 at 09:43:43AM +0900, Gyumin wrote: > Hi > > I've read the Intel 82599 official manual and I found that optimal > PTHRESH is the tx descriptor buffer size - N (N is CPU cache line > divided by 16).
This is sometimes true, but not always. I believe you are referring to section "7.2.3.4.1 Transmit Descriptor Fetch and Write-back Settings" in the datasheet. You'll see the PTHRESH, HTHRESH, and WTHRESH parameters should be tuned to for your workload. You should try a few combinations of parameters (starting with the defaults) to see which is really optimal for your application. > 1. I guess the size of the tx descriptor buffer is 128. Isn't it right? > Where is the size of the tx descriptor buffer in the official manual? The wording in the manual may be a bit confusing. You will see the manual refers to the "on-chip descriptor buffer size". This is where the NIC stores descriptors which were fetched from the actual descriptor ring in host memory. Section "7.2.3.3 Transmit Descriptor Ring" states that the size of the on-chip descriptor buffer size per queue is 40. > > 2. What it means that the TX_PTHRESH=36 in the testpmd.c? > If the size of tx descriptor buffer is 128 then optimal thresholds > to minimize latency are pthresh=4(cache line / 16), hthresh=0 and > wthresh=0. Is there something I missed? Since the on-chip descriptor buffer size is 40, it is clear that we have chosen reasonable defaults since 40 minus 4 is 36. I recommend you test a few different values to see how these parameters impact the performance characteristics of your workload. > > > Thanks. You're welcome. -Jeff
