Since SCTLR isn't allowed on userland, there is no way to detect
unalignment access support without trap.  Generally, unalignement access
causes SIGBUS, so we might get a data from crash reporter.  Android armv7-a
ABI doesn't define that hardware configuration has to set alignment bit of
SCTLR, so we should consider both unfortunately.

ARM document of Cortex-A8 says [*1], alignment identifier is 64 (VLD2.16@64),
it requires 2 cycles, but alignment identifier is 128 (VLD2.16@128), it is
1 cycle.  And on Cortex-A9, unalignment access requires additional cycles
[*2].

When I was investigating string issue, I created a benchmark result for
optimization on Cortex-A7.  So I will look for this data.


-- Makoto

[*1]
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344h/ch16s06s07.html
[*2]
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344h/ch16s06s07.html

On Tue, Mar 27, 2018 at 7:44 PM, Henri Sivonen <hsivo...@hsivonen.fi> wrote:

> I'm having trouble finding reliable information about the performance
> of unaligned NEON memory access on ARMv7 phones.
>
> What I can find is:
>
>  * ARMv7 seems to allow unaligned access to be a trap-to-kernel kind
> of performance disaster, but it's hard to find information about
> whether the phone SoCs we care about are actually disastrous like
> that.
>
>  * On aarch64, unaligned access is the same instruction as aligned
> access and gets dynamically penalized, but only minimally, if the
> access crosses a cache line boundary. *Presumably* ARMv7 code running
> on an ARMv8 core gets the same benefit.
>
> Do we know what performance characteristics we can assume for
> unaligned NEON loads/stores on Android phones that have ARMv7 cores
> and recent enough Android that Fennec runs in the first place?
>
> --
> Henri Sivonen
> hsivo...@hsivonen.fi
> https://hsivonen.fi/
> _______________________________________________
> dev-platform mailing list
> dev-platform@lists.mozilla.org
> https://lists.mozilla.org/listinfo/dev-platform
>
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