The branch main has been updated by ssaxena: URL: https://cgit.FreeBSD.org/src/commit/?id=308784bebe796cbdaccf7ef259caf7d87f874d02
commit 308784bebe796cbdaccf7ef259caf7d87f874d02 Author: Sreekanth Reddy <[email protected]> AuthorDate: 2026-06-15 09:43:01 +0000 Commit: Sumit Saxena <[email protected]> CommitDate: 2026-06-15 11:31:04 +0000 if_bnxt/bnxt_re: Update hsi headers Update hsi headers MFC after: 2 weeks Reviewed by: gallatin, ssaxena Differential Revision: https://reviews.freebsd.org/D56683 --- sys/dev/bnxt/bnxt_en/hsi_struct_def.h | 10642 +++++++++++++++++++++++++++++--- sys/dev/bnxt/bnxt_re/qplib_fp.c | 2 - sys/dev/bnxt/bnxt_re/qplib_fp.h | 1 - 3 files changed, 9668 insertions(+), 977 deletions(-) diff --git a/sys/dev/bnxt/bnxt_en/hsi_struct_def.h b/sys/dev/bnxt/bnxt_en/hsi_struct_def.h index 5914c70ce671..1bbc7b3962b9 100644 --- a/sys/dev/bnxt/bnxt_en/hsi_struct_def.h +++ b/sys/dev/bnxt/bnxt_en/hsi_struct_def.h @@ -1,7 +1,7 @@ /*- * BSD LICENSE * - * Copyright (c) 2025 Broadcom, All Rights Reserved. + * Copyright (c) 2026 Broadcom, All Rights Reserved. * The term Broadcom refers to Broadcom Limited and/or its subsidiaries * * Redistribution and use in source and binary forms, with or without @@ -31,7 +31,7 @@ __FBSDID("$FreeBSD$"); /* - * Copyright(c) 2001-2025, Broadcom. All rights reserved. The + * Copyright(c) 2001-2026, Broadcom. All rights reserved. The * term Broadcom refers to Broadcom Inc. and/or its subsidiaries. * Proprietary and Confidential Information. * @@ -119,6 +119,14 @@ typedef struct hwrm_resp_hdr { #define TLV_TYPE_QUERY_ROCE_CC_GEN2 UINT32_C(0x6) /* RoCE slow path command to modify CC Gen2 support. */ #define TLV_TYPE_MODIFY_ROCE_CC_GEN2 UINT32_C(0x7) +/* RoCE slow path command to query CC Gen1_ext support. */ +#define TLV_TYPE_QUERY_ROCE_CC_GEN1_EXT UINT32_C(0x8) +/* RoCE slow path command to modify CC Gen1_ext support. */ +#define TLV_TYPE_MODIFY_ROCE_CC_GEN1_EXT UINT32_C(0x9) +/* RoCE slow path command to query CC Gen2_ext support. */ +#define TLV_TYPE_QUERY_ROCE_CC_GEN2_EXT UINT32_C(0xa) +/* RoCE slow path command to modify CC Gen2_ext support. */ +#define TLV_TYPE_MODIFY_ROCE_CC_GEN2_EXT UINT32_C(0xb) /* Engine CKV - The Alias key EC curve and ECC public key information. */ #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001) /* Engine CKV - Initialization vector. */ @@ -370,9 +378,11 @@ typedef struct hwrm_short_input { ((x) == 0x63 ? "HWRM_RING_QCFG": \ ((x) == 0x64 ? "HWRM_RESERVED5": \ ((x) == 0x65 ? "HWRM_RESERVED6": \ + ((x) == 0x66 ? "HWRM_PORT_ADSM_QSTATES": \ + ((x) == 0x67 ? "HWRM_PORT_EVENTS_LOG": \ ((x) == 0x70 ? "HWRM_VNIC_RSS_COS_LB_CTX_ALLOC": \ ((x) == 0x71 ? "HWRM_VNIC_RSS_COS_LB_CTX_FREE": \ - "Unknown decode" ))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \ + "Unknown decode" ))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \ (((x) < 0x100) ? \ ((x) == 0x80 ? "HWRM_QUEUE_MPLS_QCAPS": \ ((x) == 0x81 ? "HWRM_QUEUE_MPLSTC2PRI_QCFG": \ @@ -420,7 +430,7 @@ typedef struct hwrm_short_input { ((x) == 0xb7 ? "HWRM_PORT_PHY_MDIO_BUS_ACQUIRE": \ ((x) == 0xb8 ? "HWRM_PORT_PHY_MDIO_BUS_RELEASE": \ ((x) == 0xb9 ? "HWRM_PORT_QSTATS_EXT_PFC_WD": \ - ((x) == 0xba ? "HWRM_RESERVED7": \ + ((x) == 0xba ? "HWRM_PORT_QSTATS_EXT_PFC_ADV": \ ((x) == 0xbb ? "HWRM_PORT_TX_FIR_CFG": \ ((x) == 0xbc ? "HWRM_PORT_TX_FIR_QCFG": \ ((x) == 0xbd ? "HWRM_PORT_ECN_QSTATS": \ @@ -461,6 +471,10 @@ typedef struct hwrm_short_input { ((x) == 0xe1 ? "HWRM_REG_POWER_QUERY": \ ((x) == 0xe2 ? "HWRM_CORE_FREQUENCY_QUERY": \ ((x) == 0xe3 ? "HWRM_REG_POWER_HISTOGRAM": \ + ((x) == 0xe4 ? "HWRM_MONITOR_PAX_HISTOGRAM_START": \ + ((x) == 0xe5 ? "HWRM_MONITOR_PAX_HISTOGRAM_COLLECT": \ + ((x) == 0xe6 ? "HWRM_STAT_QUERY_ROCE_STATS": \ + ((x) == 0xe7 ? "HWRM_STAT_QUERY_ROCE_STATS_EXT": \ ((x) == 0xf0 ? "HWRM_WOL_FILTER_ALLOC": \ ((x) == 0xf1 ? "HWRM_WOL_FILTER_FREE": \ ((x) == 0xf2 ? "HWRM_WOL_FILTER_QCFG": \ @@ -474,7 +488,7 @@ typedef struct hwrm_short_input { ((x) == 0xfa ? "HWRM_CFA_METER_INSTANCE_CFG": \ ((x) == 0xfd ? "HWRM_CFA_VFR_ALLOC": \ ((x) == 0xfe ? "HWRM_CFA_VFR_FREE": \ - "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \ + "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \ (((x) < 0x180) ? \ ((x) == 0x100 ? "HWRM_CFA_VF_PAIR_ALLOC": \ ((x) == 0x101 ? "HWRM_CFA_VF_PAIR_FREE": \ @@ -596,10 +610,9 @@ typedef struct hwrm_short_input { ((x) == 0x1b1 ? "HWRM_FUNC_LAG_UPDATE": \ ((x) == 0x1b2 ? "HWRM_FUNC_LAG_FREE": \ ((x) == 0x1b3 ? "HWRM_FUNC_LAG_QCFG": \ - ((x) == 0x1c2 ? "HWRM_FUNC_TIMEDTX_PACING_RATE_ADD": \ - ((x) == 0x1c3 ? "HWRM_FUNC_TIMEDTX_PACING_RATE_DELETE": \ - ((x) == 0x1c4 ? "HWRM_FUNC_TIMEDTX_PACING_RATE_QUERY": \ - "Unknown decode" ))))))))))))))))))))))))))))))))))))))) : \ + ((x) == 0x1c3 ? "HWRM_FUNC_TTX_PACING_RATE_PROF_QUERY": \ + ((x) == 0x1c4 ? "HWRM_FUNC_TTX_PACING_RATE_QUERY": \ + "Unknown decode" )))))))))))))))))))))))))))))))))))))) : \ (((x) < 0x280) ? \ ((x) == 0x200 ? "HWRM_SELFTEST_QLIST": \ ((x) == 0x201 ? "HWRM_SELFTEST_EXEC": \ @@ -628,8 +641,11 @@ typedef struct hwrm_short_input { ((x) == 0x218 ? "HWRM_STAT_GENERIC_QSTATS": \ ((x) == 0x219 ? "HWRM_MFG_PRVSN_EXPORT_CERT": \ ((x) == 0x21a ? "HWRM_STAT_DB_ERROR_QSTATS": \ + ((x) == 0x21b ? "HWRM_MFG_TESTS": \ + ((x) == 0x21c ? "HWRM_MFG_WRITE_CERT_NVM": \ ((x) == 0x230 ? "HWRM_PORT_POE_CFG": \ ((x) == 0x231 ? "HWRM_PORT_POE_QCFG": \ + ((x) == 0x232 ? "HWRM_PORT_PHY_FDRSTAT": \ ((x) == 0x258 ? "HWRM_UDCC_QCAPS": \ ((x) == 0x259 ? "HWRM_UDCC_CFG": \ ((x) == 0x25a ? "HWRM_UDCC_QCFG": \ @@ -642,7 +658,9 @@ typedef struct hwrm_short_input { ((x) == 0x261 ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS": \ ((x) == 0x262 ? "HWRM_QUEUE_PFCWD_TIMEOUT_CFG": \ ((x) == 0x263 ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCFG": \ - "Unknown decode" ))))))))))))))))))))))))))))))))))))))))) : \ + ((x) == 0x264 ? "HWRM_QUEUE_ADPTV_QOS_RX_QCFG": \ + ((x) == 0x265 ? "HWRM_QUEUE_ADPTV_QOS_TX_QCFG": \ + "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))) : \ (((x) < 0x300) ? \ ((x) == 0x2bc ? "HWRM_TF": \ ((x) == 0x2bd ? "HWRM_TF_VERSION_GET": \ @@ -709,7 +727,10 @@ typedef struct hwrm_short_input { ((x) == 0x399 ? "HWRM_TFC_IF_TBL_GET": \ ((x) == 0x39a ? "HWRM_TFC_TBL_SCOPE_CONFIG_GET": \ ((x) == 0x39b ? "HWRM_TFC_RESC_USAGE_QUERY": \ - "Unknown decode" )))))))))))))))))))))))))))) : \ + ((x) == 0x39c ? "HWRM_TFC_GLOBAL_ID_FREE": \ + ((x) == 0x39d ? "HWRM_TFC_TCAM_PRI_UPDATE": \ + ((x) == 0x3a0 ? "HWRM_TFC_HOT_UPGRADE_PROCESS": \ + "Unknown decode" ))))))))))))))))))))))))))))))) : \ (((x) < 0x480) ? \ ((x) == 0x400 ? "HWRM_SV": \ "Unknown decode" ) : \ @@ -747,7 +768,9 @@ typedef struct hwrm_short_input { ((x) == 0xff2c ? "HWRM_DBG_COREDUMP_CAPTURE": \ ((x) == 0xff2d ? "HWRM_DBG_PTRACE": \ ((x) == 0xff2e ? "HWRM_DBG_SIM_CABLE_STATE": \ - "Unknown decode" ))))))))))))))))))))))))))))))))) : \ + ((x) == 0xff2f ? "HWRM_DBG_TOKEN_QUERY_AUTH_IDS": \ + ((x) == 0xff30 ? "HWRM_DBG_TOKEN_CFG": \ + "Unknown decode" ))))))))))))))))))))))))))))))))))) : \ (((x) <= UINT16_MAX) ? \ ((x) == 0xffea ? "HWRM_NVM_GET_VPD_FIELD_INFO": \ ((x) == 0xffeb ? "HWRM_NVM_SET_VPD_FIELD_INFO": \ @@ -891,6 +914,8 @@ typedef struct cmd_nums { #define HWRM_RESERVED5 UINT32_C(0x64) /* Reserved for future use. */ #define HWRM_RESERVED6 UINT32_C(0x65) + #define HWRM_PORT_ADSM_QSTATES UINT32_C(0x66) + #define HWRM_PORT_EVENTS_LOG UINT32_C(0x67) #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70) #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71) #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80) @@ -944,8 +969,7 @@ typedef struct cmd_nums { #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7) #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8) #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9) - /* Reserved. */ - #define HWRM_RESERVED7 UINT32_C(0xba) + #define HWRM_PORT_QSTATS_EXT_PFC_ADV UINT32_C(0xba) #define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb) #define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc) #define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd) @@ -994,6 +1018,14 @@ typedef struct cmd_nums { #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3) + /* Start a PAX latency histogram measurement */ + #define HWRM_MONITOR_PAX_HISTOGRAM_START UINT32_C(0xe4) + /* Collect PAX latency histogram data and optionally stop measurement. */ + #define HWRM_MONITOR_PAX_HISTOGRAM_COLLECT UINT32_C(0xe5) + /* This command returns RoCE statistics for the function. */ + #define HWRM_STAT_QUERY_ROCE_STATS UINT32_C(0xe6) + /* This command returns Extended RoCE statistics for the function. */ + #define HWRM_STAT_QUERY_ROCE_STATS_EXT UINT32_C(0xe7) #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0) #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1) #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2) @@ -1257,18 +1289,16 @@ typedef struct cmd_nums { #define HWRM_FUNC_LAG_FREE UINT32_C(0x1b2) /* The command is used to query a link aggr group. */ #define HWRM_FUNC_LAG_QCFG UINT32_C(0x1b3) - /* This command is use to add TimeTX packet pacing rate. */ - #define HWRM_FUNC_TIMEDTX_PACING_RATE_ADD UINT32_C(0x1c2) /* - * This command is use to delete TimeTX packet pacing rate - * from the rate table. + * This command is used to retrieve all the TimeTX pacing rate + * profiles that are supported. */ - #define HWRM_FUNC_TIMEDTX_PACING_RATE_DELETE UINT32_C(0x1c3) + #define HWRM_FUNC_TTX_PACING_RATE_PROF_QUERY UINT32_C(0x1c3) /* * This command is used to retrieve all the TimeTX pacing rates * from the rate table that have been added for the function. */ - #define HWRM_FUNC_TIMEDTX_PACING_RATE_QUERY UINT32_C(0x1c4) + #define HWRM_FUNC_TTX_PACING_RATE_QUERY UINT32_C(0x1c4) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -1347,6 +1377,10 @@ typedef struct cmd_nums { #define HWRM_MFG_PRVSN_EXPORT_CERT UINT32_C(0x219) /* Query the statistics for doorbell drops due to various error conditions. */ #define HWRM_STAT_DB_ERROR_QSTATS UINT32_C(0x21a) + /* This command is used to select and run manufacturing tests */ + #define HWRM_MFG_TESTS UINT32_C(0x21b) + /* This command is used to write a cert chain from production firmware */ + #define HWRM_MFG_WRITE_CERT_NVM UINT32_C(0x21c) /* * The command is used to enable/disable the power on ethernet for * a particular I/O expander port. @@ -1357,6 +1391,8 @@ typedef struct cmd_nums { * is enabled/disabled for a particular I/O expander port. */ #define HWRM_PORT_POE_QCFG UINT32_C(0x231) + /* Tells the fw to run fdrstat on a given port. */ + #define HWRM_PORT_PHY_FDRSTAT UINT32_C(0x232) /* * This command returns the capabilities related to User Defined * Congestion Control on a function. @@ -1393,6 +1429,16 @@ typedef struct cmd_nums { * timeout value. */ #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG UINT32_C(0x263) + /* + * This command is used to query the current configured RX cos mbuf related + * values for a port + */ + #define HWRM_QUEUE_ADPTV_QOS_RX_QCFG UINT32_C(0x264) + /* + * This command is used to query the current configured TX cos mbuf related + * values for a port + */ + #define HWRM_QUEUE_ADPTV_QOS_TX_QCFG UINT32_C(0x265) /* Experimental */ #define HWRM_TF UINT32_C(0x2bc) /* Experimental */ @@ -1515,6 +1561,12 @@ typedef struct cmd_nums { #define HWRM_TFC_TBL_SCOPE_CONFIG_GET UINT32_C(0x39a) /* TruFlow command to query the resource usage state. */ #define HWRM_TFC_RESC_USAGE_QUERY UINT32_C(0x39b) + /* TruFlow command to free resources for a global id. */ + #define HWRM_TFC_GLOBAL_ID_FREE UINT32_C(0x39c) + /* TruFlow command to update the priority of one tcam entry. */ + #define HWRM_TFC_TCAM_PRI_UPDATE UINT32_C(0x39d) + /* TruFlow command to process hot upgrade requests. */ + #define HWRM_TFC_HOT_UPGRADE_PROCESS UINT32_C(0x3a0) /* Experimental */ #define HWRM_SV UINT32_C(0x400) /* Run a PCIe or Ethernet serdes test and retrieve test data. */ @@ -1588,6 +1640,15 @@ typedef struct cmd_nums { * or removal. */ #define HWRM_DBG_SIM_CABLE_STATE UINT32_C(0xff2e) + /* + * This command is called to obtain a board's debug authorization id (DAI) + * and token nonce (cti aka CWT ID used to prevent replay) from a NIC. + * This is the data from the device required to produce a debug enable + * token which is tied specifically to an individual NIC. + */ + #define HWRM_DBG_TOKEN_QUERY_AUTH_IDS UINT32_C(0xff2f) + /* This API is used to enable or disable a debug enable token. */ + #define HWRM_DBG_TOKEN_CFG UINT32_C(0xff30) #define HWRM_NVM_GET_VPD_FIELD_INFO UINT32_C(0xffea) #define HWRM_NVM_SET_VPD_FIELD_INFO UINT32_C(0xffeb) #define HWRM_NVM_DEFRAG UINT32_C(0xffec) @@ -1722,6 +1783,11 @@ typedef struct ret_codes { * requested by the host is not present or does not exist. */ #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT UINT32_C(0x13) + /* + * This error code is reported by Firmware when the secure soc is not + * responding. + */ + #define HWRM_ERR_CODE_SECURE_SOC_ERROR UINT32_C(0x14) /* * This value indicates that the HWRM response is in TLV format and * should be interpreted as one or more TLVs starting with the @@ -1760,7 +1826,8 @@ typedef struct ret_codes { ((x) == 0x11 ? "RESOURCE_LOCKED": \ ((x) == 0x12 ? "PF_UNAVAILABLE": \ ((x) == 0x13 ? "ENTITY_NOT_PRESENT": \ - "Unknown decode" )))))))))))))))))))) : \ + ((x) == 0x14 ? "SECURE_SOC_ERROR": \ + "Unknown decode" ))))))))))))))))))))) : \ (((x) < 0x8080) ? \ ((x) == 0x8000 ? "TLV_ENCAPSULATED_RESPONSE": \ "Unknown decode" ) : \ @@ -1848,8 +1915,8 @@ typedef struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 3 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 61 -#define HWRM_VERSION_STR "1.10.3.61" +#define HWRM_VERSION_RSVD 147 +#define HWRM_VERSION_STR "1.10.3.147" /**************** * hwrm_ver_get * @@ -2158,6 +2225,12 @@ typedef struct hwrm_ver_get_output { * feature. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_SOC_CAPABLE UINT32_C(0x10000) + /* + * If set to 1, then firmware is able to support secure debug tokens + * to enable debug on release builds. + * If set to 0, then firmware does not support debug tokens. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_DEBUG_TOKEN_SUPPORTED UINT32_C(0x20000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -9850,8 +9923,10 @@ typedef struct hwrm_async_event_cmpl { * the coredump has been captured. */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HOST_COREDUMP UINT32_C(0x50) + /* Used to notify invalid adaptive QoS configuration events. */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ADPTV_QOS UINT32_C(0x51) /* Maximum Registrable event id. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID UINT32_C(0x51) + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID UINT32_C(0x52) /* * A trace log message. This contains firmware trace logs string * embedded in the asynchronous message. This is an experimental @@ -9932,8 +10007,9 @@ typedef struct hwrm_async_event_cmpl { ((x) == 0x4e ? "REPRESENTOR_PAIR_CHANGE": \ ((x) == 0x4f ? "VF_STAT_CHANGE": \ ((x) == 0x50 ? "HOST_COREDUMP": \ - ((x) == 0x51 ? "MAX_RGTR_EVENT_ID": \ - "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))) : \ + ((x) == 0x51 ? "ADPTV_QOS": \ + ((x) == 0x52 ? "MAX_RGTR_EVENT_ID": \ + "Unknown decode" ))))))))))))))))))))))))))))))))))))))))))))))))))) : \ (((x) < 0x100) ? \ ((x) == 0xfe ? "FW_TRACE_MSG": \ ((x) == 0xff ? "HWRM_ERROR": \ @@ -12432,8 +12508,8 @@ typedef struct hwrm_async_event_cmpl_dbg_buf_producer { * value of 8192. This field rolls over to zero once the firmware * writes the last page of the host buffer */ - #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_MASK UINT32_C(0xffffffff) - #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_MASK UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_SFT 0 uint8_t opaque_v; /* * This value is written by the NIC such that it will be different @@ -12451,31 +12527,35 @@ typedef struct hwrm_async_event_cmpl_dbg_buf_producer { /* Event specific data */ uint32_t event_data1; /* Type of trace buffer that has been updated. */ - #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SFT 0 - /* SRT trace. */ - #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE UINT32_C(0x0) - /* SRT2 trace. */ + /* SRT or APE trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE UINT32_C(0x0) + /* SRT2 or AFM/Kong trace. */ #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE UINT32_C(0x1) - /* CRT trace. */ - #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE UINT32_C(0x2) - /* CRT2 trace. */ + /* CRT or ChiMP trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE UINT32_C(0x2) + /* CRT2 or Bono trace. */ #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE UINT32_C(0x3) /* RIGP0 trace. */ #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE UINT32_C(0x4) - /* L2 HWRM trace. */ + /* L2 or ChiMP HWRM trace. */ #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE UINT32_C(0x5) - /* RoCE HWRM trace. */ - #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE UINT32_C(0x6) + /* RoCE or Bono HWRM trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE UINT32_C(0x6) /* Context Accelerator CPU 0 trace. */ - #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA0_TRACE UINT32_C(0x7) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA0_TRACE UINT32_C(0x7) /* Context Accelerator CPU 1 trace. */ - #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA1_TRACE UINT32_C(0x8) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA1_TRACE UINT32_C(0x8) /* Context Accelerator CPU 2 trace. */ - #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA2_TRACE UINT32_C(0x9) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA2_TRACE UINT32_C(0x9) /* RIGP1 trace. */ #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE UINT32_C(0xa) - #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE + /* AFM/Kong HWRM trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_AFM_KONG_HWRM_TRACE UINT32_C(0xb) + /* ctxm error QPC trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ERR_QPC_TRACE UINT32_C(0xc) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ERR_QPC_TRACE } hwrm_async_event_cmpl_dbg_buf_producer_t, *phwrm_async_event_cmpl_dbg_buf_producer_t; /* hwrm_async_event_cmpl_peer_mmap_change (size:128b/16B) */ @@ -12743,7 +12823,32 @@ typedef struct hwrm_async_event_cmpl_error_report_base { * on this board. */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED UINT32_C(0x6) - #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED + /* + * In UDCC per-QP mode, NIC detects that a new QP being created has + * the same destination as an existing UDCC session. The UDCC session + * for the new QP will not be created in this error situation. + * This error normally occurs when the peer reuses the QPN of + * a destroyed QP for creating a new QP before the NIC frees + * the destroyed QP locally. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUP_UDCC_SES UINT32_C(0x7) + /* + * NIC detects that a doorbell has been dropped by hardware. + * This error normally occurs when the doorbell is mal-formatted + * by the driver or using values out of supported range by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DB_DROP UINT32_C(0x8) + /* + * Indicates the module temperature has crossed one of the thermal + * thresholds. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MD_TEMP UINT32_C(0x9) + /* + * Indicates to the host that the VNIC hw context has gone into the + * error state. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR UINT32_C(0xa) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR } hwrm_async_event_cmpl_error_report_base_t, *phwrm_async_event_cmpl_error_report_base_t; #define GET_ERROR_REPORT_TYPE(x) \ @@ -12755,7 +12860,11 @@ typedef struct hwrm_async_event_cmpl_error_report_base { ((x) == 0x4 ? "DOORBELL_DROP_THRESHOLD": \ ((x) == 0x5 ? "THERMAL_THRESHOLD": \ ((x) == 0x6 ? "DUAL_DATA_RATE_NOT_SUPPORTED": \ - "Unknown decode" ))))))) : \ + ((x) == 0x7 ? "DUP_UDCC_SES": \ + ((x) == 0x8 ? "DB_DROP": \ + ((x) == 0x9 ? "MD_TEMP": \ + ((x) == 0xa ? "VNIC_ERR": \ + "Unknown decode" ))))))))))) : \ "Unknown decode" ) @@ -13154,6 +13263,333 @@ typedef struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED } hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported_t, *phwrm_async_event_cmpl_error_report_dual_data_rate_not_supported_t; +/* hwrm_async_error_report_dup_udcc_ses (size:128b/16B) */ + +typedef struct hwrm_async_error_report_dup_udcc_ses { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_TYPE_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_TYPE_LAST HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_TYPE_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_EVENT_ID_ERROR_REPORT UINT32_C(0x45) + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_EVENT_ID_LAST HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Destination QPN of the QP being created */ + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_DST_QPN_MASK UINT32_C(0xffffff) + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_DST_QPN_SFT 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_ERROR_TYPE_MASK UINT32_C(0xff) + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_ERROR_TYPE_SFT 0 + /* + * In UDCC per-QP mode, NIC detects that a new QP being created has + * the same destination as an existing UDCC session. The UDCC session + * for the new QP will not be created in this error situation. + * This error normally occurs when the peer reuses the QPN of + * a destroyed QP for creating a new QP before the NIC frees + * the destroyed QP locally. + */ + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_ERROR_TYPE_DUP_SES UINT32_C(0x7) + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_ERROR_TYPE_LAST HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_ERROR_TYPE_DUP_SES + /* Source QPN of the QP being created */ + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_SRC_QPN_MASK UINT32_C(0xffffff00) + #define HWRM_ASYNC_ERROR_REPORT_DUP_UDCC_SES_SRC_QPN_SFT 8 +} hwrm_async_error_report_dup_udcc_ses_t, *phwrm_async_error_report_dup_udcc_ses_t; + +/* hwrm_async_error_report_db_drop (size:128b/16B) */ + +typedef struct hwrm_async_error_report_db_drop { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_TYPE_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_TYPE_LAST HWRM_ASYNC_ERROR_REPORT_DB_DROP_TYPE_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_EVENT_ID_ERROR_REPORT UINT32_C(0x45) + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_EVENT_ID_LAST HWRM_ASYNC_ERROR_REPORT_DB_DROP_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_ERROR_TYPE_MASK UINT32_C(0xff) + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_ERROR_TYPE_SFT 0 + /* + * NIC detects that a doorbell has been dropped by hardware. + * This error normally occurs when the doorbell is mal-formatted + * by the driver or using values out of supported range by hardware. + */ + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_ERROR_TYPE_DB_DROP UINT32_C(0x8) + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_ERROR_TYPE_LAST HWRM_ASYNC_ERROR_REPORT_DB_DROP_ERROR_TYPE_DB_DROP + /* + * The doorbell drops debug info. Encoded with device specific hardware + * block ID and event ID. + */ + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_DROP_DEBUG_INFO_MASK UINT32_C(0xffffff00) + #define HWRM_ASYNC_ERROR_REPORT_DB_DROP_DROP_DEBUG_INFO_SFT 8 +} hwrm_async_error_report_db_drop_t, *phwrm_async_error_report_db_drop_t; + +/* hwrm_async_error_report_md_temp (size:128b/16B) */ + +typedef struct hwrm_async_error_report_md_temp { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_TYPE_LAST HWRM_ASYNC_ERROR_REPORT_MD_TEMP_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_EVENT_ID_ERROR_REPORT UINT32_C(0x45) + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_EVENT_ID_LAST HWRM_ASYNC_ERROR_REPORT_MD_TEMP_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Current temperature. In Celsius */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_EVENT_DATA2_CUR_TEMP_MASK UINT32_C(0xff) + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_EVENT_DATA2_CUR_TEMP_SFT 0 + /* + * The temperature setting of the threshold that was just crossed. + * In Celsius + */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_EVENT_DATA2_THR_TEMP_MASK UINT32_C(0xff00) + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_EVENT_DATA2_THR_TEMP_SFT 8 + /* Indicates the module on which this temperature change occurred */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_EVENT_DATA2_MODULE_MASK UINT32_C(0xff0000) + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_EVENT_DATA2_MODULE_SFT 16 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_ERROR_TYPE_MASK UINT32_C(0xff) + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_ERROR_TYPE_SFT 0 + /* + * There was module thermal event. The type will be specified + * in the threshold_type. event_data2 will contain the current + * temperature and the configured value for the threshold that + * was just crossed. The threshold values are lower thresholds, + * so the event will trigger with an active flag when the + * temperature is on an increasing trajectory. + */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_ERROR_TYPE_MD_TEMP UINT32_C(0x9) + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_ERROR_TYPE_LAST HWRM_ASYNC_ERROR_REPORT_MD_TEMP_ERROR_TYPE_MD_TEMP + /* The specific type of thermal threshold error */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_TTYPE_MASK UINT32_C(0xff00) + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_TTYPE_SFT 8 + /* Warning thermal threshold was crossed */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_TTYPE_SFP_WARN (UINT32_C(0x0) << 8) + /* Alarm thermal threshold was crossed */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_TTYPE_SFP_ALM (UINT32_C(0x1) << 8) + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_TTYPE_LAST HWRM_ASYNC_ERROR_REPORT_MD_TEMP_TTYPE_SFP_ALM + /* + * Indicates if the thermal crossing occurs while the temperature is + * increasing or decreasing. + */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_DIR UINT32_C(0x10000) + /* Threshold is crossed while the temperature is falling. */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_DIR_FALL (UINT32_C(0x0) << 16) + /* Threshold is crossed while the temperature is rising. */ + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_DIR_RISE (UINT32_C(0x1) << 16) + #define HWRM_ASYNC_ERROR_REPORT_MD_TEMP_DIR_LAST HWRM_ASYNC_ERROR_REPORT_MD_TEMP_DIR_RISE +} hwrm_async_error_report_md_temp_t, *phwrm_async_error_report_md_temp_t; + +/* hwrm_async_error_report_vnic_err (size:128b/16B) */ + +typedef struct hwrm_async_error_report_vnic_err { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_TYPE_LAST HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_EVENT_ID_ERROR_REPORT UINT32_C(0x45) + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_EVENT_ID_LAST HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* + * The VNIC ID that was reported to the driver by firmware in + * response to HWRM_VNIC_ALLOC. + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_EVENT_DATA2_VNIC_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_EVENT_DATA2_VNIC_ID_SFT 0 + /* + * The internal firmware identifier for the VNIC + * context ID + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_EVENT_DATA2_CTXM_XID_MASK UINT32_C(0xffff0000) + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_EVENT_DATA2_CTXM_XID_SFT 16 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_ERROR_TYPE_MASK UINT32_C(0xff) + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_ERROR_TYPE_SFT 0 + /* + * Indicates to the host that the VNIC hw context has gone into the + * error state. + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_ERROR_TYPE_VNIC_ERR UINT32_C(0xa) + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_ERROR_TYPE_LAST HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_ERROR_TYPE_VNIC_ERR + /* The hardware specific error state reason. */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_MASK UINT32_C(0xff00) + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_SFT 8 + /* No error. */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_NO_ERR (UINT32_C(0x0) << 8) + /* + * A load error occurred on an attempt to load the Ring + * Table Context. + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_RT_LOAD_ERR (UINT32_C(0x1) << 8) + /* Rx Ring is not in the valid state. */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_RX_RING_ERR (UINT32_C(0x12) << 8) + /* + * Agg ring is not in the valid state and an attempt was + * made to use jumbo, HDS, or statistics ejection + * placement. + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_AGG_RING_ERR (UINT32_C(0x13) << 8) + /* + * Completion error. No space available on completion ring, + * or completion ring not in VALID state. + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_CMP_ERR (UINT32_C(0x14) << 8) + /* + * Problem was found in the format of a BD on the rx or agg + * ring. + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_BD_FORMAT_ERR (UINT32_C(0x16) << 8) + /* A packet did not fit in the buffer(s) provided. */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_DID_NOT_FIT_ERR (UINT32_C(0x17) << 8) + /* A load error occurred on an attempt to load the CQ Context. */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_CQ_LOAD_ERR (UINT32_C(0x18) << 8) + /* + * A load error occurred on an attempt to load the context for + * the rx ring, or the context loaded but the type is not l2. + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_RX_RING_LOAD_ERR (UINT32_C(0x19) << 8) + /* + * A load error occurred on the context load for the agg ring, + * or the context loaded but the type is not l2. + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_AGG_RING_LOAD_ERR (UINT32_C(0x1a) << 8) + /* + * A fatal error was detected on an attempt to read from or + * write to PCIe on the receive side. + */ + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_PCI_ERR (UINT32_C(0x1b) << 8) + #define HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_LAST HWRM_ASYNC_ERROR_REPORT_VNIC_ERR_VNIC_ERR_REASON_PCI_ERR +} hwrm_async_error_report_vnic_err_t, *phwrm_async_error_report_vnic_err_t; + /* hwrm_async_event_cmpl_vf_stat_change (size:128b/16B) */ typedef struct hwrm_async_event_cmpl_vf_stat_change { @@ -13262,6 +13698,59 @@ typedef struct hwrm_async_event_cmpl_host_coredump { uint32_t event_data1; } hwrm_async_event_cmpl_host_coredump_t, *phwrm_async_event_cmpl_host_coredump_t; +/* hwrm_async_event_cmpl_adptv_qos (size:128b/16B) */ + +typedef struct hwrm_async_event_cmpl_adptv_qos { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * Used to notify adaptive QoS configuration events. + * Firmware fallback to default settings. + */ + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_EVENT_ID_ADPTV_QOS UINT32_C(0x51) + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_EVENT_ID_ADPTV_QOS + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of invalid adaptive QoS configuration. */ + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_EVENT_DATA1_INVAL_MASK UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_EVENT_DATA1_INVAL_SFT 0 + /* + * This value indicates that the PFC headroom factor threshold value + * is out of bounds. + */ + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_EVENT_DATA1_INVAL_HEADROOM UINT32_C(0x0) + #define HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_EVENT_DATA1_INVAL_LAST HWRM_ASYNC_EVENT_CMPL_ADPTV_QOS_EVENT_DATA1_INVAL_HEADROOM +} hwrm_async_event_cmpl_adptv_qos_t, *phwrm_async_event_cmpl_adptv_qos_t; + /* metadata_base_msg (size:64b/8B) */ typedef struct metadata_base_msg { @@ -14758,6 +15247,52 @@ typedef struct hwrm_func_vf_cfg_output { uint8_t valid; } hwrm_func_vf_cfg_output_t, *phwrm_func_vf_cfg_output_t; +/* hwrm_func_vf_cfg_cmd_err (size:64b/8B) */ + +typedef struct hwrm_func_vf_cfg_cmd_err { + /* + * command specific error codes for the command + * hwrm_func_vf_cfg. + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Failed to perform TX ring asset test. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_TX_RING_ASSET_TEST_FAILED UINT32_C(0x1) + /* Failed to update TX ring PF reservation. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_TX_RING_RES_UPDATE_FAILED UINT32_C(0x2) + /* Failed to perform RSSCOS context asset test. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_RSS_CTXT_ASSET_TEST_FAILED UINT32_C(0x3) + /* Failed to update RSSCOS context PF reservation. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_RSS_CTXT_RES_UPDATE_FAILED UINT32_C(0x4) + /* Failed to perform completion ring asset test. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_CMPL_RING_ASSET_TEST_FAILED UINT32_C(0x5) + /* Failed to update completion ring PF reservation. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_CMPL_RING_RES_UPDATE_FAILED UINT32_C(0x6) + /* Failed to perform RX ring asset test. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_RX_RING_ASSET_TEST_FAILED UINT32_C(0x7) + /* Failed to update RX ring PF reservation. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_RX_RING_RES_UPDATE_FAILED UINT32_C(0x8) + /* Failed to perform VNIC asset test. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_VNIC_ASSET_TEST_FAILED UINT32_C(0x9) + /* Failed to update VNIC ring PF reservation. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_VNIC_RES_UPDATE_FAILED UINT32_C(0xa) + /* Failed to sync and start STATS thread. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_SYNC_STATS_THREAD_FAILED UINT32_C(0xb) + /* Not enough l2_ctxt_entries available for the VF. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_L2_CTXT_RES_ALLOC_FAILED UINT32_C(0xc) + /* Failed to update TX KTLS PF reservation. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_TX_KTLS_RES_UPDATE_FAILED UINT32_C(0xd) + /* Failed to update RX KTLS PF reservation. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_RX_KTLS_RES_UPDATE_FAILED UINT32_C(0xe) + /* Failed to update TX QUIC PF reservation. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_TX_QUIC_RES_UPDATE_FAILED UINT32_C(0xf) + /* Failed to update RX QUIC PF reservation. */ + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_RX_QUIC_RES_UPDATE_FAILED UINT32_C(0x10) + #define HWRM_FUNC_VF_CFG_CMD_ERR_CODE_LAST HWRM_FUNC_VF_CFG_CMD_ERR_CODE_RX_QUIC_RES_UPDATE_FAILED + uint8_t unused_0[7]; +} hwrm_func_vf_cfg_cmd_err_t, *phwrm_func_vf_cfg_cmd_err_t; + /******************* * hwrm_func_qcaps * *******************/ @@ -15075,9 +15610,7 @@ typedef struct hwrm_func_qcaps_output { /* * The maximum number of VFs that can be * allocated to the function. This is valid only on the - * PF with SR-IOV enabled. 0xFF... (All Fs) if this - * command is called on a PF with SR-IOV disabled or - * on a VF. + * PF with SR-IOV enabled. */ uint16_t max_vfs; /* @@ -15687,8 +16220,88 @@ typedef struct hwrm_func_qcaps_output { * if the driver tries to set the reservation to be less than the * number of allocated resources. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP UINT32_C(0x1) - uint8_t unused_3[7]; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP UINT32_C(0x1) + /* + * When this bit is '1', the PF requires an L2 filter to be + * allocated by the driver using HWRM_CFA_L2_FILTER_ALLOC after + * bringing the interface up, before traffic is sent. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_REQUIRE_L2_FILTER UINT32_C(0x2) + /* + * When set to 1, indicates the field max_roce_vfs in the structure + * is valid. If this bit is 0, the driver should not use the + * 'max_roce_vfs' field. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED UINT32_C(0x4) + /* + * When set to 1, indicates the field 'rx_rate_profile_sel' in + * RING_ALLOC can specify a valid RX rate profile when allocating + * RX or RX aggregation rings. If this bit is 0, the driver + * should not use the 'rx_rate_profile_sel' field. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_RX_RATE_PROFILE_SEL_SUPPORTED UINT32_C(0x8) + /* + * When set to 1, indicates that the device is capable of supporting + * the RoCE bi-directional optimization feature. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_BIDI_OPT_SUPPORTED UINT32_C(0x10) + /* + * When set to 1, indicates that the device is capable of supporting + * port mirroring on RoCE device. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_MIRROR_ON_ROCE_SUPPORTED UINT32_C(0x20) + /* + * When set to 1, indicates that the PF is capable of supporting + * dynamic distribution of RoCE resources amongst its VFs + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_ROCE_VF_DYN_ALLOC_SUPPORT UINT32_C(0x40) + /* + * When set to 1, indicates that the device supports changing UDP + * source port of RoCEv2 packets + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_CHANGE_UDP_SRCPORT_SUPPORT UINT32_C(0x80) + /* + * When set to 1, indicates that the device supports enabling or + * disabling pcie compliance. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_PCIE_COMPLIANCE_SUPPORTED UINT32_C(0x100) + /* + * When this bit is '1', it indicates that, when rx/tx/cq/nq l2 + * rings are allocated, each ring can be associated with a + * non-common doorbell page index. When '0', a common doorbell + * page is used for all rings on a PF. This bit is only set on a + * PF. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_MULTI_L2_DB_SUPPORTED UINT32_C(0x200) + /* + * When this bit is '1', it indicates that the firmware supports + * PCIe secure ATS solution. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_PCIE_SECURE_ATS_SUPPORTED UINT32_C(0x400) + /* *** 12097 LINES SKIPPED ***
