The branch main has been updated by cperciva:
URL:
https://cgit.FreeBSD.org/src/commit/?id=4322d597453d63d638675b8612d7aaabd65dcadd
commit 4322d597453d63d638675b8612d7aaabd65dcadd
Author: David Woodhouse <d...@amazon.co.uk>
AuthorDate: 2025-07-31 07:33:54 +0000
Commit: Colin Percival <cperc...@freebsd.org>
CommitDate: 2025-08-13 20:31:15 +0000
bhyve: Support and advertise 15-bit MSI Extended Destination ID
To support guests with more than 255 vCPUs, allow bits 5-11 of the MSI
address to be used as additional destination ID bits. This is compatible
with Hyper-V, KVM and Xen's implementation of the same enlightenment, as
documented at http://david.woodhou.se/ExtDestId.pdf
Reviewed by: kib
Pull Request: https://github.com/freebsd/freebsd-src/pull/1797
Signed-off-by: David Woodhouse <d...@amazon.co.uk>
---
sys/amd64/vmm/io/vioapic.c | 9 +++++++++
sys/amd64/vmm/vmm_lapic.c | 5 +++++
sys/amd64/vmm/x86.c | 2 +-
sys/x86/include/apicreg.h | 2 ++
4 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/sys/amd64/vmm/io/vioapic.c b/sys/amd64/vmm/io/vioapic.c
index 8869dc1383e6..7df6193d6dc0 100644
--- a/sys/amd64/vmm/io/vioapic.c
+++ b/sys/amd64/vmm/io/vioapic.c
@@ -130,6 +130,15 @@ vioapic_send_intr(struct vioapic *vioapic, int pin)
vector = low & IOART_INTVEC;
dest = high >> APIC_ID_SHIFT;
+ /*
+ * Ideally we'd just call lapic_intr_msi() here with the
+ * constructed MSI instead of interpreting it for ourselves.
+ * But until/unless we support emulated IOMMUs with interrupt
+ * remapping, interpretation is simple. We just need to mask
+ * in the Extended Destination ID bits for the 15-bit
+ * enlightenment (http://david.woodhou.se/ExtDestId.pdf)
+ */
+ dest |= ((high & APIC_EXT_ID_MASK) >> APIC_EXT_ID_SHIFT) << 8;
vlapic_deliver_intr(vioapic->vm, level, dest, phys, delmode, vector);
}
diff --git a/sys/amd64/vmm/vmm_lapic.c b/sys/amd64/vmm/vmm_lapic.c
index fd511733492e..0cae01f172ec 100644
--- a/sys/amd64/vmm/vmm_lapic.c
+++ b/sys/amd64/vmm/vmm_lapic.c
@@ -115,6 +115,11 @@ lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg)
* physical otherwise.
*/
dest = (addr >> 12) & 0xff;
+ /*
+ * Extended Destination ID support uses bits 5-11 of the address:
+ * http://david.woodhou.se/ExtDestId.pdf
+ */
+ dest |= ((addr >> 5) & 0x7f) << 8;
phys = ((addr & (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)) !=
(MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG));
delmode = msg & APIC_DELMODE_MASK;
diff --git a/sys/amd64/vmm/x86.c b/sys/amd64/vmm/x86.c
index 9c2fdac11a81..2e2224595ab4 100644
--- a/sys/amd64/vmm/x86.c
+++ b/sys/amd64/vmm/x86.c
@@ -614,7 +614,7 @@ x86_emulate_cpuid(struct vcpu *vcpu, uint64_t *rax,
uint64_t *rbx,
break;
case CPUID_BHYVE_FEATURES:
- regs[0] = 0; /* No features to advertise yet */
+ regs[0] = CPUID_BHYVE_FEAT_EXT_DEST_ID;
regs[1] = 0;
regs[2] = 0;
regs[3] = 0;
diff --git a/sys/x86/include/apicreg.h b/sys/x86/include/apicreg.h
index d610d7f11a1c..1252647fbab3 100644
--- a/sys/x86/include/apicreg.h
+++ b/sys/x86/include/apicreg.h
@@ -296,6 +296,8 @@ typedef struct IOAPIC ioapic_t;
/* constants relating to APIC ID registers */
#define APIC_ID_MASK 0xff000000
#define APIC_ID_SHIFT 24
+#define APIC_EXT_ID_MASK 0x00fe0000
+#define APIC_EXT_ID_SHIFT 17
#define APIC_ID_CLUSTER 0xf0
#define APIC_ID_CLUSTER_ID 0x0f
#define APIC_MAX_CLUSTER 0xe
