The branch main has been updated by andrew:
URL:
https://cgit.FreeBSD.org/src/commit/?id=6ff9bb7c3bb089a85af067c4159cd942f204ba76
commit 6ff9bb7c3bb089a85af067c4159cd942f204ba76
Author: Andrew Turner <and...@freebsd.org>
AuthorDate: 2025-07-31 14:12:34 +0000
Commit: Andrew Turner <and...@freebsd.org>
CommitDate: 2025-07-31 14:27:06 +0000
arm64: Use a fixed value for sctlr_el1
We load a fixed value into sctlr_el1 in enter_kernel_el so there is no
need to clear and set fields. Replace with a fixed list of fields that
are set when the MMU is off an when it is on.
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D51011
---
sys/arm64/arm64/locore.S | 23 +++--------------------
sys/arm64/include/armreg.h | 20 ++++++++++++++++++++
2 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index f200195906ac..4a10a2b4f2d3 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -319,14 +319,12 @@ LEND(mpentry_common)
* - Configure EL2 to support running the kernel at EL1 and exit to that
*/
LENTRY(enter_kernel_el)
-#define INIT_SCTLR_EL1 (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_EIS | \
- SCTLR_TSCXT | SCTLR_EOS)
mrs x23, CurrentEL
and x23, x23, #(CURRENTEL_EL_MASK)
cmp x23, #(CURRENTEL_EL_EL2)
b.eq 1f
- ldr x2, =INIT_SCTLR_EL1
+ ldr x2, =SCTLR_MMU_OFF
msr sctlr_el1, x2
/* SCTLR_EOS is set so eret is a context synchronizing event so we
* need an isb here to ensure it's observed by later instructions,
@@ -370,7 +368,7 @@ LENTRY(enter_kernel_el)
msr vmpidr_el2, x2
/* Set the initial sctlr_el1 */
- ldr x2, =INIT_SCTLR_EL1
+ ldr x2, =SCTLR_MMU_OFF
msr sctlr_el1, x2
/* Check for VHE */
@@ -442,7 +440,6 @@ LENTRY(enter_kernel_el)
isb
eret
-#undef INIT_SCTLR_EL1
LEND(enter_kernel_el)
/*
@@ -1037,11 +1034,7 @@ LENTRY(start_mmu)
/*
* Setup SCTLR.
*/
- ldr x2, sctlr_set
- ldr x3, sctlr_clear
- mrs x1, sctlr_el1
- bic x1, x1, x3 /* Clear the required bits */
- orr x1, x1, x2 /* Set the required bits */
+ ldr x1, =SCTLR_MMU_ON
msr sctlr_el1, x1
isb
@@ -1066,16 +1059,6 @@ tcr:
.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG | \
TCR_SH1_IS | TCR_ORGN1_WBWA | TCR_IRGN1_WBWA | \
TCR_SH0_IS | TCR_ORGN0_WBWA | TCR_IRGN0_WBWA)
-sctlr_set:
- /* Bits to set */
- .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \
- SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \
- SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \
- SCTLR_M | SCTLR_CP15BEN | SCTLR_BT1 | SCTLR_BT0)
-sctlr_clear:
- /* Bits to clear */
- .quad (SCTLR_EE | SCTLR_E0E | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \
- SCTLR_ITD | SCTLR_A)
LEND(start_mmu)
ENTRY(abort)
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 38b7f57f7853..500f35c48787 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -2608,6 +2608,26 @@
#define SCTLR_EnALS (UL(0x1) << 56)
#define SCTLR_EPAN (UL(0x1) << 57)
+#define SCTLR_MMU_OFF \
+ (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_EIS | SCTLR_TSCXT | SCTLR_EOS)
+#define SCTLR_MMU_ON \
+ (SCTLR_MMU_OFF | \
+ SCTLR_BT1 | \
+ SCTLR_BT0 | \
+ SCTLR_UCI | \
+ SCTLR_SPAN | \
+ SCTLR_nTWE | \
+ SCTLR_nTWI | \
+ SCTLR_UCT | \
+ SCTLR_DZE | \
+ SCTLR_I | \
+ SCTLR_SED | \
+ SCTLR_CP15BEN | \
+ SCTLR_SA0 | \
+ SCTLR_SA | \
+ SCTLR_C | \
+ SCTLR_M)
+
/* SCTLR_EL12 */
#define SCTLR_EL12_REG MRS_REG_ALT_NAME(SCTLR_EL12)
#define SCTLR_EL12_op0 3
