The branch main has been updated by andrew:
URL:
https://cgit.FreeBSD.org/src/commit/?id=8986e15f0bb524fdb2414240e0df67d911f2fabc
commit 8986e15f0bb524fdb2414240e0df67d911f2fabc
Author: Andrew Turner <and...@freebsd.org>
AuthorDate: 2025-07-30 22:07:03 +0000
Commit: Andrew Turner <and...@freebsd.org>
CommitDate: 2025-07-30 22:33:26 +0000
arm64: Teach CHECK_CPU_FEAT to handle more values
CHECK_CPU_FEAT only supported checking for features that were enabled
when the field is non-zero. There are some features we might need to
check where we move between two non-zero values.
Support this by passing in the field value name to compare rather than
assuming a non-zero value.
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D51375
---
sys/arm64/arm64/locore.S | 8 ++++----
sys/arm64/include/asm.h | 7 ++++---
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index bb323dbafd85..47c609fad523 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -374,7 +374,7 @@ LENTRY(enter_kernel_el)
msr sctlr_el1, x2
/* Check for VHE */
- CHECK_CPU_FEAT(x2, ID_AA64MMFR1, VH, .Lno_vhe)
+ CHECK_CPU_FEAT(x2, ID_AA64MMFR1, VH, IMPL, .Lno_vhe)
/*
* The kernel will be running in EL2, route exceptions here rather
@@ -413,7 +413,7 @@ LENTRY(enter_kernel_el)
* Configure the Extended Hypervisor register. This is only valid if
* FEAT_HCX is enabled.
*/
- CHECK_CPU_FEAT(x2, ID_AA64MMFR1, HCX, 2f)
+ CHECK_CPU_FEAT(x2, ID_AA64MMFR1, HCX, IMPL, 2f)
/* Extended Hypervisor Configuration */
mov x2, xzr
msr HCRX_EL2_REG, x2
@@ -430,7 +430,7 @@ LENTRY(enter_kernel_el)
msr vttbr_el2, xzr
/* Check the CPU supports GIC, and configure the CPU interface */
- CHECK_CPU_FEAT(x2, ID_AA64PFR0, GIC, 3f)
+ CHECK_CPU_FEAT(x2, ID_AA64PFR0, GIC, CPUIF_EN, 3f)
mrs x2, icc_sre_el2
orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */
@@ -1029,7 +1029,7 @@ LENTRY(start_mmu)
* HW management of dirty state is set in C code as it may
* need to be disabled because of CPU errata.
*/
- CHECK_CPU_FEAT(x3, ID_AA64MMFR1, HAFDBS, 1f)
+ CHECK_CPU_FEAT(x3, ID_AA64MMFR1, HAFDBS, AF, 1f)
orr x2, x2, #(TCR_HA)
1:
diff --git a/sys/arm64/include/asm.h b/sys/arm64/include/asm.h
index 4f373dc4b7e1..f9a64f574fca 100644
--- a/sys/arm64/include/asm.h
+++ b/sys/arm64/include/asm.h
@@ -77,10 +77,11 @@
* to the given label. The tmp register should be a register able to hold the
* temporary data.
*/
-#define CHECK_CPU_FEAT(tmp, feat_reg, feat, label) \
- mrs tmp, ##feat_reg##_el1; \
+#define CHECK_CPU_FEAT(tmp, feat_reg, feat, min_val, label) \
+ mrs tmp, ##feat_reg##_el1; \
ubfx tmp, tmp, ##feat_reg##_##feat##_SHIFT,
##feat_reg##_##feat##_WIDTH; \
- cbz tmp, label
+ cmp tmp, #(##feat_reg##_##feat##_##min_val## >>
##feat_reg##_##feat##_SHIFT); \
+ b.lt label
/*
* Sets the trap fault handler. The exception handler will return to the
