The branch main has been updated by mhorne:
URL:
https://cgit.FreeBSD.org/src/commit/?id=134f7b5fa91fa41e3c3c7caeaf1dff72018684e5
commit 134f7b5fa91fa41e3c3c7caeaf1dff72018684e5
Author: Mitchell Horne <mho...@freebsd.org>
AuthorDate: 2024-06-03 17:24:12 +0000
Commit: Mitchell Horne <mho...@freebsd.org>
CommitDate: 2024-06-14 18:02:05 +0000
riscv: improve commentary around initial stvec
Make it explicit why we must set the trap vector before enabling virtual
memory.
Reviewed by: br, jhb, markj
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D45474
---
sys/riscv/riscv/locore.S | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/sys/riscv/riscv/locore.S b/sys/riscv/riscv/locore.S
index 5a7e15ba443b..7e885ab8ca89 100644
--- a/sys/riscv/riscv/locore.S
+++ b/sys/riscv/riscv/locore.S
@@ -197,7 +197,11 @@ pagetables:
/* Page tables END */
- /* Setup supervisor trap vector */
+ /*
+ * Set the supervisor trap vector temporarily. Enabling virtual memory
+ * may generate a page fault. We simply wish to continue onwards, so
+ * have the trap deliver us to 'va'.
+ */
2:
lla t0, va
sub t0, t0, s9
@@ -221,7 +225,7 @@ va:
lla gp, __global_pointer$
.option pop
- /* Setup supervisor trap vector */
+ /* Set the trap vector to the real handler. */
la t0, cpu_exception_handler
csrw stvec, t0
@@ -342,7 +346,11 @@ ENTRY(mpentry)
/* Get the kernel's load address */
jal get_physmem
- /* Setup supervisor trap vector */
+ /*
+ * Set the supervisor trap vector temporarily. Enabling virtual memory
+ * may generate a page fault. We simply wish to continue onwards, so
+ * have the trap deliver us to 'mpva'.
+ */
lla t0, mpva
sub t0, t0, s9
li t1, KERNBASE
@@ -365,7 +373,7 @@ mpva:
lla gp, __global_pointer$
.option pop
- /* Setup supervisor trap vector */
+ /* Set the trap vector to the real handler. */
la t0, cpu_exception_handler
csrw stvec, t0
