On 6/2/24 13:43, Jessica Clarke wrote:
     fu740_pci_dw: Fix PERST delay and keep asserted for rest of reset sequence
DELAY takes microseconds not milliseconds, so 100 was too low. Moreover,
     when enabling hw.pci.clear_pcib, PCI emeration would still stop at one
     of the first bridges, but by asserting PERST for the rest of the reset
     sequence that appears to be reliably addressed.

Does this need to be a DELAY as opposed to something asynchronous?  We try to
avoid lengthy DELAYs in the boot process.

--
Colin Percival
FreeBSD Release Engineering Lead & EC2 platform maintainer
Founder, Tarsnap | www.tarsnap.com | Online backups for the truly paranoid

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