The branch main has been updated by mhorne:
URL:
https://cgit.FreeBSD.org/src/commit/?id=7245ffd10eda4ff604840350943d762f70657983
commit 7245ffd10eda4ff604840350943d762f70657983
Author: Mitchell Horne <mho...@freebsd.org>
AuthorDate: 2023-05-22 23:53:43 +0000
Commit: Mitchell Horne <mho...@freebsd.org>
CommitDate: 2023-05-23 13:19:26 +0000
riscv: MMU detection
Detect and report the supported MMU for each CPU. Export the
capabilities to the rest of the kernel and use it in pmap_bootstrap() to
check for Sv48 support.
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D39814
---
sys/riscv/include/cpu.h | 8 ++++++++
sys/riscv/include/md_var.h | 1 +
sys/riscv/riscv/identcpu.c | 30 ++++++++++++++++++++++++++++++
sys/riscv/riscv/pmap.c | 2 +-
4 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/sys/riscv/include/cpu.h b/sys/riscv/include/cpu.h
index b7d83aa0f25d..d99142bc3c93 100644
--- a/sys/riscv/include/cpu.h
+++ b/sys/riscv/include/cpu.h
@@ -83,6 +83,14 @@
/* SiFive marchid values */
#define MARCHID_SIFIVE_U7 MARCHID_COMMERCIAL(7)
+/*
+ * MMU virtual-addressing modes. Support for each level implies the previous,
+ * so Sv48-enabled systems MUST support Sv39, etc.
+ */
+#define MMU_SV39 0x1 /* 3-level paging */
+#define MMU_SV48 0x2 /* 4-level paging */
+#define MMU_SV57 0x4 /* 5-level paging */
+
extern char btext[];
extern char etext[];
diff --git a/sys/riscv/include/md_var.h b/sys/riscv/include/md_var.h
index 890f569782a3..687ab9a3a77e 100644
--- a/sys/riscv/include/md_var.h
+++ b/sys/riscv/include/md_var.h
@@ -40,6 +40,7 @@ extern u_long elf_hwcap;
extern register_t mvendorid;
extern register_t marchid;
extern register_t mimpid;
+extern u_int mmu_caps;
struct dumperinfo;
struct minidumpstate;
diff --git a/sys/riscv/riscv/identcpu.c b/sys/riscv/riscv/identcpu.c
index d4ad8a1078b6..01e9fe9b4669 100644
--- a/sys/riscv/riscv/identcpu.c
+++ b/sys/riscv/riscv/identcpu.c
@@ -65,10 +65,13 @@ register_t mvendorid; /* The CPU's JEDEC vendor ID */
register_t marchid; /* The architecture ID */
register_t mimpid; /* The implementation ID */
+u_int mmu_caps;
+
struct cpu_desc {
const char *cpu_mvendor_name;
const char *cpu_march_name;
u_int isa_extensions; /* Single-letter extensions. */
+ u_int mmu_caps;
};
struct cpu_desc cpu_desc[MAXCPU];
@@ -269,6 +272,20 @@ parse_riscv_isa(struct cpu_desc *desc, char *isa, int len)
}
#ifdef FDT
+static void
+parse_mmu_fdt(struct cpu_desc *desc, phandle_t node)
+{
+ char mmu[16];
+
+ desc->mmu_caps |= MMU_SV39;
+ if (OF_getprop(node, "mmu-type", mmu, sizeof(mmu)) > 0) {
+ if (strcmp(mmu, "riscv,sv48") == 0)
+ desc->mmu_caps |= MMU_SV48;
+ else if (strcmp(mmu, "riscv,sv57") == 0)
+ desc->mmu_caps |= MMU_SV48 | MMU_SV57;
+ }
+}
+
static void
identify_cpu_features_fdt(u_int cpu, struct cpu_desc *desc)
{
@@ -317,6 +334,9 @@ identify_cpu_features_fdt(u_int cpu, struct cpu_desc *desc)
if (parse_riscv_isa(desc, isa, len) != 0)
return;
+ /* Check MMU features. */
+ parse_mmu_fdt(desc, node);
+
/* We are done. */
break;
}
@@ -356,6 +376,11 @@ update_global_capabilities(u_int cpu, struct cpu_desc
*desc)
/* Update the capabilities exposed to userspace via AT_HWCAP. */
UPDATE_CAP(elf_hwcap, (u_long)desc->isa_extensions);
+ /*
+ * MMU capabilities, e.g. Sv48.
+ */
+ UPDATE_CAP(mmu_caps, desc->mmu_caps);
+
#undef UPDATE_CAP
}
@@ -429,6 +454,11 @@ printcpuinfo(u_int cpu)
desc->cpu_mvendor_name, desc->cpu_march_name, hart);
printf(" marchid=%#lx, mimpid=%#lx\n", marchid, mimpid);
+ printf(" MMU: %#b\n", desc->mmu_caps,
+ "\020"
+ "\01Sv39"
+ "\02Sv48"
+ "\03Sv57");
printf(" ISA: %#b\n", desc->isa_extensions,
"\020"
"\01Atomic"
diff --git a/sys/riscv/riscv/pmap.c b/sys/riscv/riscv/pmap.c
index 8d34dbc3637d..007ec1e678fc 100644
--- a/sys/riscv/riscv/pmap.c
+++ b/sys/riscv/riscv/pmap.c
@@ -704,7 +704,7 @@ pmap_bootstrap(vm_offset_t l1pt, vm_paddr_t kernstart,
vm_size_t kernlen)
mode = 0;
TUNABLE_INT_FETCH("vm.pmap.mode", &mode);
- if (mode == PMAP_MODE_SV48) {
+ if (mode == PMAP_MODE_SV48 && (mmu_caps & MMU_SV48) != 0) {
/*
* Enable SV48 mode: allocate an L0 page and set SV48 mode in
* SATP. If the implementation does not provide SV48 mode,
