The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=f711d5c3d06677740dc04a0ced27b2bce894bae1
commit f711d5c3d06677740dc04a0ced27b2bce894bae1 Author: Mitchell Horne <[email protected]> AuthorDate: 2023-01-10 15:50:00 +0000 Commit: Mitchell Horne <[email protected]> CommitDate: 2023-02-06 19:26:53 +0000 libdtrace: add riscv support Largely untested, as we can't really do anything with user probes without an implementation of fasttrap. However, this is enough to generate an embedded dtrace program with `dtrace -G` and link the generated ELF file. Reviewed by: markj Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D38301 --- .../opensolaris/lib/libdtrace/common/dt_link.c | 110 +++++++++++++++++++-- 1 file changed, 103 insertions(+), 7 deletions(-) diff --git a/cddl/contrib/opensolaris/lib/libdtrace/common/dt_link.c b/cddl/contrib/opensolaris/lib/libdtrace/common/dt_link.c index 4e7935250620..51f853d9a2b8 100644 --- a/cddl/contrib/opensolaris/lib/libdtrace/common/dt_link.c +++ b/cddl/contrib/opensolaris/lib/libdtrace/common/dt_link.c @@ -225,9 +225,9 @@ prepare_elf32(dtrace_hdl_t *dtp, const dof_hdr_t *dof, dof_elf32_t *dep) rel->r_info = ELF32_R_INFO(count + dep->de_global, R_PPC_REL32); #elif defined(__riscv) -/* XXX */ - printf("%s:%s(%d): RISC-V not implemented\n", - __FUNCTION__, __FILE__, __LINE__); + rel->r_offset = s->dofs_offset + dofr[j].dofr_offset; + rel->r_info = ELF32_R_INFO(count + dep->de_global, + R_RISCV_32_PCREL); #else #error unknown ISA #endif @@ -403,7 +403,9 @@ prepare_elf64(dtrace_hdl_t *dtp, const dof_hdr_t *dof, dof_elf64_t *dep) rel->r_info = ELF64_R_INFO(count + dep->de_global, R_PPC64_REL64); #elif defined(__riscv) -/* XXX */ + rel->r_offset = s->dofs_offset + dofr[j].dofr_offset; + rel->r_info = ELF64_R_INFO(count + dep->de_global, + R_RISCV_32_PCREL); #elif defined(__i386) || defined(__amd64) rel->r_offset = s->dofs_offset + dofr[j].dofr_offset; @@ -504,6 +506,22 @@ dump_elf32(dtrace_hdl_t *dtp, const dof_hdr_t *dof, int fd) elf_file.ehdr.e_machine = EM_386; #elif defined(__aarch64__) elf_file.ehdr.e_machine = EM_AARCH64; +#elif defined(__riscv) + elf_file.ehdr.e_machine = EM_RISCV; + + /* Set the ELF flags according to our current ABI */ +#if defined(__riscv_compressed) + elf_file.ehdr.e_flags |= EF_RISCV_RVC; +#endif +#if defined(__riscv_float_abi_soft) + elf_file.ehdr.e_flags |= EF_RISCV_FLOAT_ABI_SOFT; +#endif +#if defined(__riscv_float_abi_single) + elf_file.ehdr.e_flags |= EF_RISCV_FLOAT_ABI_SINGLE; +#endif +#if defined(__riscv_float_abi_double) + elf_file.ehdr.e_flags |= EF_RISCV_FLOAT_ABI_DOUBLE; +#endif #endif elf_file.ehdr.e_version = EV_CURRENT; elf_file.ehdr.e_shoff = sizeof (Elf32_Ehdr); @@ -645,6 +663,22 @@ dump_elf64(dtrace_hdl_t *dtp, const dof_hdr_t *dof, int fd) elf_file.ehdr.e_machine = EM_AMD64; #elif defined(__aarch64__) elf_file.ehdr.e_machine = EM_AARCH64; +#elif defined(__riscv) + elf_file.ehdr.e_machine = EM_RISCV; + + /* Set the ELF flags according to our current ABI */ +#if defined(__riscv_compressed) + elf_file.ehdr.e_flags |= EF_RISCV_RVC; +#endif +#if defined(__riscv_float_abi_soft) + elf_file.ehdr.e_flags |= EF_RISCV_FLOAT_ABI_SOFT; +#endif +#if defined(__riscv_float_abi_single) + elf_file.ehdr.e_flags |= EF_RISCV_FLOAT_ABI_SINGLE; +#endif +#if defined(__riscv_float_abi_double) + elf_file.ehdr.e_flags |= EF_RISCV_FLOAT_ABI_DOUBLE; +#endif #endif elf_file.ehdr.e_version = EV_CURRENT; elf_file.ehdr.e_shoff = sizeof (Elf64_Ehdr); @@ -917,14 +951,74 @@ dt_modtext(dtrace_hdl_t *dtp, char *p, int isenabled, GElf_Rela *rela, return (0); } #elif defined(__riscv) +#define DT_OP_NOP 0x00000013 /* addi x0, x0, 0 */ +#define DT_OP_RET 0x00008067 /* jalr x0, x1, 0 */ +#define DT_OP_IS_AUIPC(op) (((op) & 0x7f) == 0x17) +#define DT_OP_IS_JALR(op) (((op) & 0x707f) == 0x67) +#define DT_OP_JALR_CALL 0x000080e7 /* jalr x1, x1, 0 */ +#define DT_OP_JALR_TAIL 0x00030067 /* jalr x0, x6, 0 */ #define DT_REL_NONE R_RISCV_NONE + static int dt_modtext(dtrace_hdl_t *dtp, char *p, int isenabled, GElf_Rela *rela, uint32_t *off) { - printf("%s:%s(%d): RISC-V implementation required\n", __FUNCTION__, - __FILE__, __LINE__); - return (-1); + uint32_t *ip; + + /* + * XXX: this implementation is untested, but should serve as a decent + * starting point. + */ + + /* + * Ensure that the offset is aligned on a compressed-instruction + * boundary. + */ + if ((rela->r_offset & (sizeof (uint16_t) - 1)) != 0) + return (-1); + + /* + * We only know about some specific relocation types. + * We also recognize relocation type NONE, since that gets used for + * relocations of USDT probes, and we might be re-processing a file. + */ + if (GELF_R_TYPE(rela->r_info) != R_RISCV_CALL && + GELF_R_TYPE(rela->r_info) != R_RISCV_CALL_PLT && + GELF_R_TYPE(rela->r_info) != R_RISCV_NONE) + return (-1); + + ip = (uint32_t *)(p + rela->r_offset); + + /* + * We may have already processed this object file in an earlier linker + * invocation. Check to see if the present instruction sequence matches + * the one we would install below. + */ + if (ip[0] == DT_OP_NOP && (ip[1] == DT_OP_NOP || ip[1] == DT_OP_RET)) + return (0); + + /* + * We expect a auipc+jalr pair, either from a call or a tail. + * - call: auipc x1 0; jalr x1, x1, 0 + * - tail: auipc x6 0; jalr x0, x6, 0 + */ + if (!DT_OP_IS_AUIPC(ip[0]) || !DT_OP_IS_JALR(ip[1])) + return (-1); + + /* + * On riscv, we do not have to differentiate between regular probes and + * is-enabled probes. Calls are to be converted into a no-op whereas + * tail calls should become a return. + */ + if (ip[1] == DT_OP_JALR_CALL) { + ip[0] = DT_OP_NOP; + ip[1] = DT_OP_NOP; + } else { + ip[0] = DT_OP_NOP; + ip[1] = DT_OP_RET; + } + + return (0); } #elif defined(__i386) || defined(__amd64) @@ -1155,6 +1249,8 @@ process_obj(dtrace_hdl_t *dtp, const char *obj, int *eprobesp) emachine1 = emachine2 = EM_AMD64; #elif defined(__aarch64__) emachine1 = emachine2 = EM_AARCH64; +#elif defined(__riscv) + emachine1 = emachine2 = EM_RISCV; #endif symsize = sizeof (Elf64_Sym); } else {
