The branch main has been updated by andrew:
URL:
https://cgit.FreeBSD.org/src/commit/?id=f62e099ed51bf15ebafa20a044e106480547a0ad
commit f62e099ed51bf15ebafa20a044e106480547a0ad
Author: Andrew Turner <and...@freebsd.org>
AuthorDate: 2022-03-10 10:54:39 +0000
Commit: Andrew Turner <and...@freebsd.org>
CommitDate: 2022-03-10 10:54:39 +0000
Fix the TCR_TG0 values
They are in a different order to the TCR_TG1 values but appear to have
been copied incorrectly.
While here use TCR_TG0_4K in locore.S to make it explicit the userspace
page size is 4K.
Sponsored by: The FreeBSD Foundation
---
sys/arm64/arm64/locore.S | 2 +-
sys/arm64/include/armreg.h | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index d72747f0896d..c9cf25aae37f 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -742,7 +742,7 @@ mair:
MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) | \
MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE)
tcr:
- .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | \
+ .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | TCR_TG0_4K | \
TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
sctlr_set:
/* Bits to set */
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index cd09807ec4be..5d9172cd3d6b 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -1404,9 +1404,9 @@
#define TCR_T1SZ_SHIFT 16
#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT)
#define TCR_TG0_SHIFT 14
-#define TCR_TG0_16K (1UL << TCR_TG0_SHIFT)
-#define TCR_TG0_4K (2UL << TCR_TG0_SHIFT)
-#define TCR_TG0_64K (3UL << TCR_TG0_SHIFT)
+#define TCR_TG0_4K (0UL << TCR_TG0_SHIFT)
+#define TCR_TG0_64K (1UL << TCR_TG0_SHIFT)
+#define TCR_TG0_16K (2UL << TCR_TG0_SHIFT)
#define TCR_SH0_SHIFT 12
#define TCR_SH0_IS (3UL << TCR_SH0_SHIFT)
#define TCR_ORGN0_SHIFT 10
