The branch main has been updated by kbowling (ports committer):
URL:
https://cgit.FreeBSD.org/src/commit/?id=de965d042fa4d341cec3fa7cacac0f30f224bde4
commit de965d042fa4d341cec3fa7cacac0f30f224bde4
Author: Guinan Sun <guinanx....@intel.com>
AuthorDate: 2020-07-06 08:12:16 +0000
Commit: Kevin Bowling <kbowl...@freebsd.org>
CommitDate: 2021-09-17 21:23:26 +0000
e1000: expose FEXTNVM registers and masks
Adding defines for FEXTNVM8 and FEXTNVM12 registers with new masks for
future use.
Signed-off-by: Nir Efrati <nir.efr...@intel.com>
Signed-off-by: Guinan Sun <guinanx....@intel.com>
Reviewed-by: Wei Zhao <wei.zh...@intel.com>
Approved by: imp
Obtained from: DPDK (6d208ec099cd870a73c6b444b350a82c7a26c5e4)
MFC after: 1 week
---
sys/dev/e1000/e1000_ich8lan.h | 3 ++-
sys/dev/e1000/e1000_regs.h | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/sys/dev/e1000/e1000_ich8lan.h b/sys/dev/e1000/e1000_ich8lan.h
index 12f912ebc6e0..caff11cbb899 100644
--- a/sys/dev/e1000/e1000_ich8lan.h
+++ b/sys/dev/e1000/e1000_ich8lan.h
@@ -113,11 +113,12 @@
#define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000
#define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004
#define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
+#define E1000_FEXTNVM8_UNBIND_DPG_FROM_MPHY 0x00000400
#define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800
#define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000
#define E1000_FEXTNVM11_DISABLE_PB_READ 0x00000200
#define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000
-
+#define E1000_FEXTNVM12_DONT_WAK_DPG_CLKREQ 0x00001000
/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
#define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000
diff --git a/sys/dev/e1000/e1000_regs.h b/sys/dev/e1000/e1000_regs.h
index fe9834405359..01009d969620 100644
--- a/sys/dev/e1000/e1000_regs.h
+++ b/sys/dev/e1000/e1000_regs.h
@@ -66,8 +66,10 @@
#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
#define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */
#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
+#define E1000_FEXTNVM8 0x5BB0 /* Future Extended NVM 8 - RW */
#define E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */
#define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */
+#define E1000_FEXTNVM12 0x5BC0 /* Future Extended NVM 12 - RW */
#define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */
#define E1000_FCT 0x00030 /* Flow Control Type - RW */
#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
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